Method of fabricating a SRAM device

Details Method of fabricating a SRAM device Method of fabricating a SRAM device

2001-07-02

2002-08-13

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S383000, C438S384000, C438S385000

Reexamination Certificate

active

06432766

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating SRAM devices and, more particularly, to a method of forming a contact of a SRAM device which exhibits reduced contact resistance.
2. Description of Related Art
Generally, semiconductor memory devices are broadly classified into DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) according to their memory mode.
SRAMs are widely used memory devices, which may be driven at high speed while providing low power consumption and simple operation. Moreover, SRAMs, unlike DRAMs, do not require that the stored information be periodically refreshed and are relatively easy to design.
SRAM cells are typically composed of two pull-down devices (hereinafter referred to as drive transistors), two access devices (access transistors) and two pull-up devices. Depending on the construction of the pull-up devices, these SRAM cells may be classified into three main types, a full CMOS type, a High Load Resistor (HLR) type and a Thin Film Transistor (TFT) type.
The full CMOS type cell employs a P-channel bulk MOSFET as the pull-up device, the HLR type cell employs a polysilicon layer, and the TFT type cell employs a P-channel polysilicon TFT.
A conventional method of fabricating a HLR type SRAM device will now be schematically described with reference to
FIG. 1
which is a cross-sectional view showing a HLR type SRAM device.
Referring to
FIG. 1
, the conventional method for fabricating the HLR type SRAM device includes forming a gate insulating film
3
on a semiconductor substrate
1
having a field oxide film
2
providing isolation between adjacent devices. Using known deposition techniques, a first polysilicon film is deposited on the gate insulating film.
Then, the first polysilicon film is patterned and etched to form a gate electrode
4
A of an access transistor and a gate electrode
4
B of a drive transistor.
Next, spacers
5
are formed on both sidewalls of the respective gate electrodes
4
A and
4
B, and impurity ions are implanted into the semiconductor substrate
1
at both sides of the gate electrodes
4
A and
4
B to form the source
6
A and drain
6
B regions of the transistors.
In
FIG. 1
, the source region
6
A is a common connection node to which the access transistor, the drive transistor and a high load resistor (not shown) are connected, and the drain region
6
B is a region to which a bit line is connected.
After this, a first interlayer insulating film
7
is deposited on the resulting substrate. The first interlayer insulating film is then partially etched so as to expose the drain region
6
B of the access transistor.
A second polysilicon film is then deposited in such a manner that it is in contact with the exposed drain region
6
B. The second polysilicon film is then patterned and etched to form a bit contact buffer region
8
.
Afterwards, a second interlayer insulating film
9
is formed on the bit contact buffer region
8
and the first interlayer insulating film
7
, after which the first and second interlayer insulating films
7
and
9
are etched in such a manner that the source region
6
A, i.e., the common node of the drive transistor and the access transistor, is exposed. As a result, a contact hole
9
A is formed. When forming the contact hole H, the gate electrode
4
B of the drive transistor is partially exposed.
Next, an undoped third polysilicon film
10
is deposited on the second interlayer insulating film
9
in such a manner that it contacts both the exposed source region
6
A and the gate electrode
4
B of the drive transistor.
Following this, the third polysilicon film
10
is patterned, and impurity ions are implanted into the majority of the third polysilicon film, e.g., that portion of the film that will provide the connection lines between the devices, thereby forming a source voltage line
10
A, an undoped high load resistor portion
10
B and a connection line
10
C.
However, the conventional method of fabricating the SRAM device suffers from certain problems. For example, in the conventional method described above, the source voltage line, the high load resistor portion and the connection line are formed by depositing an undoped polysilicon film and then selectively implanting impurity ions into selected portions of the polysilicon film corresponding to the source voltage line and the connection line.
After the above ion implantation is complete, a heat treatment is carried out to activate the implanted ions. As a result of this heat treatment, the final resistance value becomes smaller than the designed resistance value.
In addition, because the diffusion length is a direct function of the heat treatment temperature and duration, there is a limit to how much the width of the resistor may be reduced in order to increase the integration density.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to solve the problems with the prior art and to provide a method of fabricating a SRAM device, which includes forming the source voltage lines and connection lines using a silicide process and thus forming source voltage and connection lines having lower resistance.
To achieve the above object, the present invention provides a method of fabricating a SRAM device, comprising the steps of: providing a semiconductor substrate having a field oxide film and a first polysilicon film; patterning the polysilicon film to form a gate electrode for an access transistor and a gate electrode for a drive transistor; implanting an impurity into the substrate at both sides of the respective gate electrodes to form source and drain regions; forming a silicide film on the source region of the access transistor; forming a first interlayer insulating film on the resulting semiconductor substrate; patterning the first interlayer insulating film in such a manner that a portion of the drain region of the access transistor and a portion of the source region, i.e., the portion that serves as a common node for the drive transistor and the access transistor, are exposed; depositing a second polysilicon film on the resulting semiconductor substrate; polishing the second polysilicon film using a chemical mechanical polishing (CMP) process to expose the first interlayer insulating film, thereby forming a polysilicon plug and a bit contact buffer region; forming a second interlayer insulating film on the semiconductor substrate on which the polysilicon plug and the bit contact buffer region were formed; patterning the second interlayer insulating film so as to expose the polysilicon plug; forming a third polysilicon film on the patterned second interlayer insulating film; depositing an insulating film on the third polysilicon film and patterning the insulating film in such a manner that those portions of the third polysilicon film intended for the source voltage lines and connection lines are exposed; and forming a metal thin film on the exposed portions of the third polysilicon film and thermally treating the resulting substrate to form the source voltage lines and the connection lines.


REFERENCES:
patent: 6245611 (2001-06-01), Hahsimoto et al.
patent: 6255151 (2001-07-01), Fukuda et al.
patent: 6258649 (2001-07-01), Nakamura et al.
patent: 6171898 (2002-01-01), Crenshaw et al.
patent: 6342416 (2002-01-01), Kim et al.

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