Method of fabricating a split-gate semiconductor device

Details Method of fabricating a split-gate semiconductor device Method of fabricating a split-gate semiconductor device

2002-08-28

2004-03-16

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S952000

Reexamination Certificate

active

06706600

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, more particularly to methods of forming and removing floating gates in the fabrication of a semiconductor device having transistors with a split-gate structure.
2. Description of the Related Art
The split-gate structure is used in, for example, low-voltage electrically erasable programmable read-only memory (EEPROM). As shown in
FIG. 6
, a memory cell in this type of semiconductor device
100
comprises a field-effect transistor having a floating gate
101
and control gate
102
disposed side by side above the channel between the source (SRC) and drain (DRN). In this example, the drain includes a heavily doped N
+
-type region and a more lightly doped N-type region, and the floating gate
101
also extends over the lightly doped N-type region. As shown, the source and drain may be shared with adjacent memory cells. The control gates
102
are insulated by a dielectric layer
103
.
In one known split-gate fabrication process, the control gates
102
are formed first, as shown in
FIG. 7A
, the upper surface of each control gate
102
being covered by the dielectric layer
103
. Typically, the control gates
102
have a thickness of two hundred fifty to four hundred nanometers (250-400 nm), and the dielectric layer
103
has a thickness of one hundred to two hundred nanometers (100-200 nm). As shown in
FIG. 7B
, a thin oxide film
104
and a thin nitride film
105
are deposited; then an etching mask is formed and the nitride film
105
is partially removed by etching in preparation for ion implantation, which forms the N
+
source regions. Next, as shown in
FIG. 7C
, a layer of polycrystalline silicon
106
(generally referred to as polysilicon or simply ‘poly’) is deposited and etched down to the height of the control gates
102
and their overlying dielectric layer, leaving polysilicon floating gates disposed in the desired areas, on the sidewalls of the control gates
102
.
Other fabrication steps, such as the drain formation steps, have been omitted from the above description for simplicity.
One problem with this fabrication process is that at the stage shown in
FIG. 7C
, polysilicon material is also left over the N
+
source regions. The polysilicon material may react with the underlying substrate material in a way that impairs the properties of the N
+
source regions. Furthermore, depending on the dimensions of the source regions, the polysilicon may fail to fill the slits between adjacent control gates, which is troublesome in subsequent fabrication steps.
Another problem is that if the polysilicon layer
106
is etched by a dry etching process using conventional etching techniques, exposed oxide material may be removed and the dielectric layer protecting the control gates
102
may be etched. This problem does not occur if a wet etching process is used, but wet etching cannot form the desired floating gate structure on the sidewalls of the control gates
102
.
Yet another problem is that after the floating gates have been formed, some of them must be removed by further etching, to create transistors without floating gates. Such transistors are needed in peripheral circuits, for example. Once the floating gates have been implanted, however, they are not easily removed by either wet or dry etching without damage to other parts of the device or the creation of height irregularities.
SUMMARY OF THE INVENTION
An object of the present invention is accordingly to provide a fabrication process that can etch unwanted floating-gate material from a split-gate semiconductor device without damaging desired control-gate material.
Another object is to reduce the height differential between transistors that retain their floating gates and transistors from which the floating gates are removed.
Yet another object is to provide a fabrication process that can etch oxide films in control gate structures without etching field oxide material.
According to one aspect of the invention, a semiconductor device having a plurality of transistors, some of the transistors having split gates including respective control gates and floating gates, other transistors having only control gates, is fabricated by forming the control gates of the transistors, forming an oxide film and a nitride film covering the sidewalls of the control gates, forming floating gates on the covered sidewalls of the control gates, forming a bottom anti-reflective coating, and removing unwanted ones of the floating gates, using the bottom anti-reflective coating as a mask.
The control gates may include a dielectric layer such as a non-silicate glass layer or a nitride layer. The unwanted floating gates are preferably etched isotropically, using a gaseous mixture of carbon tetrafluoride, chlorine, and oxygen that etches the floating-gate material more rapidly than the dielectric material, so that the control gate material is protected by the dielectric layer during the etching process.
This process enables floating gates to be formed and removed without creating great differences in height between transistors with floating gates and transistors without floating gates. Floating gates may be created simultaneously on both the source and drain sides of the control gates.
According to another aspect of the invention, a split-gate semiconductor device is fabricated by forming a first oxide film on a substrate, forming a control gate layer on the first oxide film, forming a non-silicate glass layer on the control gate layer, forming a silicon nitride layer on the non-silicate glass layer, and selectively etching these layers by dry etching to form control gate structures. Each control gate structure includes a control gate part, a non-silicate glass part, and two silicon nitride parts. The upper surfaces and sidewalls of the control gate structures and the spaces between them are covered with a second oxide film and a silicon nitride film. A first polysilicon film is formed and etched to leave polysilicon covering the sidewalls of the control gate structures. P-type and N-type regions are formed in the substrate, the remaining part of the first polysilicon film is removed by wet etching, and the second oxide film and silicon nitride film are removed from the spaces between the control gate structures. A third oxide film is formed on the upper surfaces and sidewalls of the control gate structures and the spaces between them, and a second polysilicon film is formed on the third oxide film. The second polysilicon film is selectively removed by dry etching, leaving floating gates on the sidewalls of the control gate structures. The central parts of the control gate structures are then removed by etching, leaving control gates with floating gates formed on one sidewall.
This process enables floating gates of arbitrary size to be formed on the sidewalls of the control gates. When the central parts of the control gates are etched, a bottom anti-reflective coating can be used to protect the field oxide areas, enabling the conditions for etching the oxide film within the control gate structures to be controlled to achieve optimal etching of the control gate structures, without the unwanted removal of control gate material or field oxide material.


REFERENCES:
patent: 5298446 (1994-03-01), Onishi et al.
patent: 5930627 (1999-07-01), Zhou et al.
patent: 6022776 (2000-02-01), Lien et al.
Wolf et al., “Silicon Processing for the VLSI Era vol. 1: Process Technology”, pp. 547-557, Lattice Press, 1986, pp. 547-557.

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