Method of fabricating a split-gate flash memory

Details Method of fabricating a split-gate flash memory Method of fabricating a split-gate flash memory

1999-12-03

2001-03-13

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S266000, C438S593000, C438S594000

Reexamination Certificate

active

06200859

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application ser. no. 88119924, filed Nov. 16, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for fabricating a flash memory, and more particularly, to a method for fabricating a split-gate flash memory.
2. Description of the Related Art
At present, nonvolatile memory is widely used in the whole range of electrical devices. In particular, programmable nonvolatile memory having a flash memory structure such as the erasable programmable read-only memory and electrically erased programmable read-only memory has attracted immense interest. In general, a flash memory comprises two gates, a floating gate for charge storage and a control gate for data accessing. The floating gate is in a floating state without being connected to any electrical circuit and is located between the control gate and a substrate while the control gate is connected to a word line.
FIG. 1
is a schematic, cross-sectional view showing a structure of a split-gate flash memory according to the prior art. In the
FIG. 1
, a floating gate
102
and a control gate
104
are formed on a substrate
100
. A split-gate oxide layer
106
and a dielectric layer
108
separate the floating gate
102
and the control gate
104
. Source/drain regions
110
a
,
110
b
are respectively formed in the substrate
100
adjacent to the collective structure of the control gate
104
and the floating gate
102
. Sometimes, the control gate
104
is referred to as a selective gate. Referring to
FIG. 1
, the semiconductor process is first to form the floating gate
102
on the substrate
100
and then to form the split-gate oxide layer
106
. Subsequently, a conductive layer is formed on the split-gate oxide layer
106
. Then, the conductive layer is defined into the control gate
104
as shown in
FIG. 1
by photolithography and etching. Afterwards, an ion implantation process is performed to form the source/drain regions
110
a
,
110
b
. A distance L
1
covered by the control gate
104
between the source/drain region
110
a
and the structure comprising the dielectric layer
108
and the floating gate
102
is referred to as a channel length of the selective gate.
According to the prior art, the process is first to form the control gate
104
and then to form the source/drain region
110
a
; thus, the channel length L
1
of the selective gate depends on the accuracy of photolithography for defining the control gate
104
. Thus, when the photomask used for defining the control gate
104
is misaligned and the control gate
104
formed is shifted from a desired position, the channel length L
1
is increased or decreased, and the reading current and the programming current are varied with the length L
1
. When the length L
1
is increased, the reading current is reduced; thus, a sensitive sense amplifier is required for detecting the reading current. In addition, the programming current is also reduced while the length L
1
is increased; thus, the time for programming is increased, the speed becomes slower, and the operation time is increased.
SUMMARY OF THE INVENTION
According to above, the invention provides a method for fabricating a split-gate flash memory. According to the invention, a drain region and a floating gate are formed before a selective gate is formed in order to fix the distance between the drain region and the floating gate and to decide a channel length thereby. Thus, the invention can stably provide a reading current and a programming current and enhance the reliability of a device.
The invention provides a method for fabricating a split-gate flash memory. The method comprises the following steps.
A tunnelling oxide layer, a first conductive layer, and a hard mask layer are formed on a substrate in sequence. A drain opening and a floating gate opening are formed on the hard mask layer by defining the hard mask layer in order to expose the first conductive layer. A first polyoxide layer and a second polyoxide layer are formed on the first conductive layer exposed by the drain opening and the floating gate opening, respectively. The first polyoxide layer and the first conductive layer beneath the first polyoxide layer are removed to expose the substrate in the drain opening. A drain is formed in the substrate in the drain opening. The hard mask layer is removed, and the first conductive layer is etched into a floating gate using the second polyoxide layer as a mask. A split-gate oxide layer and a second conductive layer are formed on the resulting structure in sequence. A control gate is formed by defining the second conductive layer, and a source region beside the floating gate is formed in the substrate.
The invention provides another option for the method of fabricating a split-gate flash memory. The option comprises the following steps.
A tunnelling oxide layer, a first conductive layer, and a hard mask layer are formed on a substrate in sequence. A drain opening and a floating gate opening are formed on the hard mask layer by defining the hard mask layer in order to expose the first conductive layer. The first conductive layer exposed in the drain opening is removed to expose the substrate. A drain is formed in the substrate exposed by the drain opening, and an oxide layer is formed on the drain region. A polyoxide layer is formed on the first conductive layer exposed by the floating gate opening. The hard mask layer is removed, and the first conductive layer is etched into a floating gate using the second polyoxide layer as a mask. A split-gate oxide layer and a second conductive layer are formed on the resulting structure in sequence. A control gate is formed by defining the second conductive layer, and a source region beside the floating gate is formed in the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5278087 (1994-01-01), Jenq
patent: 5879992 (1999-03-01), Hsieh et al.
patent: 5940706 (1999-08-01), Sung et al.
patent: 5970371 (1999-10-01), Hsieh et al.
patent: 6069042 (2000-05-01), Chien et al.
patent: 6093608 (2000-07-01), Lin et al.
patent: 6121088 (2000-09-01), Lin et al.

Affiliated with

Also associated with

Rating

Method of fabricating a split-gate flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a split-gate flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a split-gate flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2478331