Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-18
2001-07-31
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S423000, C438S433000, C257S401000
Reexamination Certificate
active
06268248
ABSTRACT:
BACKGROUND OF THE INVENTION
Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are typically constructed from various microelectronic devices fabricated on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a pattern of conductor, semiconductor, and insulator regions formed on the semiconductor substrate.
The density of the microelectronic devices on the semiconductor substrate may be increased by decreasing spacing between each of the various semiconductor devices. The decrease in spacing allows a larger number of such microelectronic devices to be formed on the semiconductor substrate. As a result, the computing power and speed of the semiconductor component may be greatly improved.
FLASH memory, also known as FLASH EPROM or FLASH EEPROM, is a semiconductor component that is formed from an array of memory cells with each cell having a floating gate transistor. Data can be written to each cell within the array, but the data is erased in blocks of cells. Each cell is a floating gate transistor having a source, drain, floating gate, and a control gate. The floating gate uses channel hot electrons for writing from the drain and uses Fowler-Nordheim tunneling for erasure from the source. The sources of each floating gate in each cell in a row of the array are connected to form a source line.
The floating gate transistors are electrically isolated from one another by an isolation structure. One type of isolation structure used is a LOCal Oxidation of Silicon (LOCOS) structure. LOCOS structures are generally formed by thermally growing a localized oxidation layer between the cells to electrically isolate the cells. One problem with the LOCOS structure is that the structure includes non-functional areas that waste valuable space on the semiconductor substrate.
Another type of isolation structure used is a Shallow Trench Isolation (STI). STI structures are generally formed by etching a trench between the, cells and filling the trench with a suitable dielectric material. STI structures are smaller than LOCOS structures and allow the cells to be spaced closer together to increase the density of cells in the array. However, STI structures are often not used in FLASH memory due to the difficulty in forming the source line that connects the cells in each row. The source line in FLASH memory utilizing STI structures often has a higher resistance than a corresponding FLASH memory that uses LOCOS structures. The increased electrical resistance reduces the operational performance of the memory.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an improved source line for flash memory using an STI structure and method of construction. The present invention provides an improved source line for flash memory using an STI structure and method of construction that substantially eliminates or reduces problems associated with the prior methods and systems.
In accordance with one embodiment of the present invention an improved method of forming a semiconductor device component having a conductive line that crosses a trench includes forming the trench in a semiconductor substrate. A dopant is implanted at a first energy level into the semiconductor substrate to form a first conductive region. The dopant is also implanted at a second energy level into the semiconductor substrate to form a second conductive region wherein the first energy level is greater than the second energy level. The first and second conductive regions together form the conductive line.
Important technical advantages of the present invention include fabricating a source line with shallow trench isolation structures, wherein the source line has an electrical resistance that is comparable with that of a source line fabricated by some conventional processes. In addition, the electrical resistance of the source line may be lower than that of a corresponding source line fabricated using a LOCOS isolation structure.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
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Brady III W. James
Chaudhuri Olik
Coleman William David
McLarty Peter K.
Telecky , Jr. Frederick J.
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