Method of fabricating a sonos device

Details Method of fabricating a sonos device Method of fabricating a sonos device

2001-11-20

2002-10-01

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S261000, C438S591000, C438S954000

Reexamination Certificate

active

06458642

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90126670, filed Oct. 29, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a semiconductor process, particularly to a method of fabricating a SONOS (Substrate/Oxide/Nitride/Oxide/Silicon) device.
2. Description of Related Art
FIG. 1
illustrates a cross sectional view of a conventional SONOS device.
Refer to
FIG. 1
, a word-line
104
is disposed on a substrate
100
and an ONO (Oxide/Nitride/Oxide) composite layer
102
is located between the word-line
104
and the substrate
100
to act as a trapping layer. Buried bit-lines
106
are disposed in the substrate
100
beside the ONO layer
102
, while buried bit-line oxide layers
108
are located on the buried bit-lines
106
to separate the buried bit-lines
106
and the word-lines
104
.
However, the dopants in the buried bit-lines
106
that are normally formed by ion implantation easily diffuse during the thermal process. The effective channel length of the device is thus decreased and the short channel effect is consequently induced. The short channel effect becomes even more severe when the device is scaled down.
Therefore, another method of making a SONOS device is provided to solve the above-mentioned problems, wherein a pocket doped region is used as an isolation for the buried bit-line
106
.
FIGS.
2
A~
2
C are cross sectional views illustrating the process flow of fabricating a SONOS device in the prior art.
Refer to
FIG. 2A
, an ONO composite layer
202
is first formed on a substrate
200
, then a mask pattern
210
is formed on the ONO layer
202
. A pocket ion implantation
212
is then performed to form doped pocket regions
214
in the substrate
200
beside the ONO layer
202
by using the mask pattern
210
as a mask. The pocket ion implantation
212
must be performed in large angle, so as to enable the pocket doped region
214
to reach under the side-wall of the ONO layer
202
.
Refer to
FIG. 2B
, another ion implantation
216
is conducted to form buried bit-lines
206
in the substrate
200
beside the ONO layer
202
by using the mask pattern
210
as a mask.
Refer to
FIG. 2C
, the mask pattern
210
is removed, then a thermal process is conducted to form the buried bit-line oxide layers
218
on the buried bit-lines
206
by using the ONO layer
202
as a mask. Finally, a word-line
204
is formed over the substrate
200
.
However, since the buried bit-lines
206
and the pocket doped regions
214
are formed with the same ONO layer
202
as their implantation masks, the pocket ion implantation
212
must be conducted in large angle, thus the implantation process is more complicated and less reliable. In addition, the pocket doped regions
214
such formed cannot well cover the buried bit-line
206
. The punch-through phenomenon thereby easily occurs.
SUMMARY OF THE INVENTION
Accordingly, a method of fabricating a SONOS is provided in this invention to prevent the short channel effect caused by diffusion of the dopants in the buried bit-lines during the thermal process.
The invention also provides a method of fabricating a SONOS device, wherein the pocket doped region is formed at the periphery of the buried bit-line and well covers the buried bit-line to avoid the punch-through phenomenon.
According to a preferred embodiment of the present invention provides of fabricating a SONOS device, a first silicon oxide layer, a trapping layer, and a second silicon oxide layer are sequentially formed on the substrate. A mask pattern is formed on the second silicon oxide layer to serve as a mask in the following implantation process for forming the buried bit-lines. Afterward, a portion of the mask pattern, the second oxide layer and the trapping layer exposed by the mask pattern are removed by, for example, isotropic etching back to increase the gap size of the mask pattern and expose a portion of the first oxide layer. A pocket ion implantation is then performed to form a pocket doped region at the periphery of the buried bit-line by using the mask pattern as a mask. Subsequently, the mask pattern is removed and a thermal process is conducted using the trapping layer as a mask to form a buried bit-line oxide layer, then a word-line is formed over the substrate.
This invention also provides a method of fabricating a NROM (Nitride ROM) device. A first oxide layer, a trapping layer, and a second oxide layer are sequentially formed on the substrate. A gate pattern is formed on the second oxide layer to serve as a mask in the following implantation process for forming the buried bit-lines. Afterward, a portion of the gate pattern, the second oxide layer and the trapping layer exposed by the gate pattern are removed by, for example, isotropic etching back to increase the gap size of the gate pattern and expose a portion of the first oxide layer. A pocket ion implantation is then performed to form a pocket doped region at the periphery of the buried bit-line by using the gate pattern as a mask. Subsequently, a thermal process is conducted by using the trapping layer as a mask to form a buried bit-line oxide layer on the buried bit-line, then a word-line is formed over the substrate.
According to the present invention, a mask pattern with a smaller gap size is used as the implantation mask for making the buried bit-line and then the mask pattern is isotropically etched to serve as a mask in the pocket ion implantation process. Since the buried bit-line is formed with the mask pattern having a smaller gap size, the short channel effect caused by diffusion of the dopants in the buried bit-line can be prevented and the effective channel length is increased. Meanwhile, the gap size of the mask pattern is increased by an isotropic etching-back process. The pocket doped region can thereby be formed at the periphery of the buried bit-line to avoid the punch-through phenomenon.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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