Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-06
2001-08-21
Bowers, Charles (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S149000, C438S151000
Reexamination Certificate
active
06277684
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device using a SOI (Silicon On Insulator) substrate, and more particularly to a device structure in which this feature is employed in the silicon layer portion of the semiconductor device.
In a SOI substrate, a silicon layer is formed on a layer with insulation properties, a so-called BOX oxide layer. This silicon layer is isolated by a trench structure or a LOCOS (Local Oxidation of Silicon) method in order to isolate the device. The trench method in which a groove is formed by the silicon layer being etched and an oxide layer being deposited in the groove is disclosed in “IEEE ELECTRON DEVICE LETTERS, VOL. 6, JUNE, 1995,” and others. The cost of isolation using the trench structure is high because the number of processes required for trench structure formation is greater than the LOCOS method.
The device isolation for SOI by the LOCOS method is disclosed in “Proceedings IEEE Intr. SOI conf., 116 (1995).” According to the LOCOS method, a thin silicon layer the sectional shape of which is a triangle is formed between a LOCOS oxide layer and a BOX oxide layer and this layer forms the parasite MOSFET. This parasite MOSFET influences significantly the current property of the original (on the assumption that there is no MOSFET) MOSFET. This influence is called a bump property because it looks like a bump is made on the current properties. The threshold voltage for which the parasite MOSFET exists is lower than the original MOSFET.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor device of SOI structure which cannot easily form a parasite MOSFET.
To achieve the above described object, a SOI structure semiconductor device includes a silicon substrate, an insulating oxide layer formed on the silicon substrate, a SOI layer formed on the insulating oxide layer a LOCOS oxide layer formed on the insulating oxide layer and contacting with the SOI layer in order to insulate the SOI layer, a gate insulation layer formed on the SOI layer and a gate electrode formed on the gate insulation layer. The SOI layer has a sectional triangle portion contacting with the LOCOS oxide layer. The sectional triangle has an oblique side as a boundary between the SOI layer and the LOCOS oxide layer, a height side equal to the thickness of the SOI layer and a base on the lower boundary of the SOI layer, in which the ratio of the height side to the base is 4:1 or less.
REFERENCES:
patent: 4842675 (1989-06-01), Chapman et al.
patent: 5504034 (1996-04-01), Rapisarda et al.
patent: 5736451 (1998-04-01), Gayet
patent: 5814551 (1998-09-01), Park et al.
patent: 5837378 (1998-11-01), Mathews et al.
patent: 5874325 (1999-02-01), Koike
patent: 6033941 (2000-03-01), Yang
patent: 6087241 (2000-07-01), St Amand et al.
patent: 019548076A1 (1996-06-01), None
patent: 000442296A2 (1991-08-01), None
patent: 001049172A2 (2000-02-01), None
Fukuda Kouichi
Hayashi Hirokazu
Miura Noriyuki
Blum David S
Bowers Charles
Jones Volentine PLLC
OKI Electric Industry Co., Ltd.
LandOfFree
Method of fabricating a SOI structure semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a SOI structure semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a SOI structure semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2494323