Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-05
2001-06-05
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06242295
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of microelectronic devices, and more particularly to a method of fabricating a shallow doped region for a shallow junction transistor.
BACKGROUND OF THE INVENTION
Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are typically constructed from various microelectronic devices fabricated on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a pattern of conductor, semiconductor, and insulator regions formed on the semiconductor substrate.
The density of the microelectronic devices on the semiconductor substrate may be increased by decreasing the size, or linewidth, of the various semiconductor devices. The decrease in linewidth allows a larger number of such microelectronic devices to be formed on the semiconductor substrate. As a result, the computing power and speed of the semiconductor component may be greatly improved.
In order to decrease the linewidth of the microelectronic device, the size and thickness of the conductor, semiconductor, and insulator regions forming each microelectronic device must be reduced. As the size of the microelectronic device is scaled down to sub-micron sizes, there is a need to form shallow doped regions in the semiconductor substrate. For example, a shallow doped region may be used to construct a shallow junction transistor. Shallow junction transistors are less susceptible to current leakage and the formation of unwanted parasitic connections and devices.
Some techniques for fabricating a shallow doped region include the use of an ion beam to shallowly implant a dopant into the semiconductor substrate. As is well known to those in the art, the ion implantation process generally operates by ionizing and accelerating dopant atoms into the semiconductor substrate. The dopant atoms are thereby implanted into the semiconductor substrate. The doped region of the semiconductor substrate generally forms a conductive region, such as a source or drain component of a transistor.
The ion implantation process often damages the crystal lattice of the semiconductor substrate being implanted. In the case of shallow doped regions, ion implantation damage generally has a greater adverse affect because the size of the doped region is small. For example, damage to the source and drain regions of a shallow junction transistor may result in an increase in the leakage and in the threshold voltage of the transistor, thereby decreasing the performance of the transistor.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for an improved method of fabricating a shallow doped region for a shallow junction transistor. The present invention provides an improved method of fabricating a shallow doped region for a shallow junction transistor that substantially eliminates or reduces problems associated with the prior methods and systems.
In accordance with one embodiment of the present invention, a method of fabricating a shallow doped region in a substrate for a shallow junction transistor is provided. The method comprising the steps of providing a substrate having a first region and a second region. The first region and the second region include a first channel region and a second channel region, respectively. A first gate is formed proximate the first channel region and is separated from the substrate by a portion of a primary insulation layer. A second gate is formed proximate the second channel region and separated from the substrate by a portion of the primary insulation layer. A dopant layer is then formed outwardly of the substrate proximate the first and second regions. The dopant layer proximate the first region is implanted with a first dopant. The dopant layer proximate the second region is implanted with a second dopant. A portion of the first dopant in the dopant layer is diffused into the substrate proximate the first region to form a first shallow doped region, and a portion of the second dopant in the dopant layer is diffused into the substrate proximate the second region to form a second shallow doped region.
Important technical advantages of the present invention include providing a shallow doped region that is not damaged during an ion implantation process. In the case of a shallow junction transistor, the present invention allows the fabrication of a source and drain that are undamaged by ion implantation. Accordingly, the diode leakage and the threshold voltage of the shallow junction transistor may be reduced, thereby increasing the performance of the transistor.
Yet another technical advantage of the present invention includes providing a transistor having shallower drain and source regions. Accordingly, the linewidth of the microelectronic devices may be decreased. Thus, the present invention may allow the fabrication of transistors that are smaller than can be attained by some fabrication techniques.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 4599789 (1986-07-01), Gasner
patent: 5242847 (1993-09-01), Ozturk et al.
Grider Douglas T.
Rodder Mark S.
Violette Katherine
Brady III W. James
Hoang Quoc
McLarty Peter K.
Nelms David
Telecky , Jr. Frederick J.
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