Method of fabricating a semiconductor memory device

Details Method of fabricating a semiconductor memory device Method of fabricating a semiconductor memory device

1997-08-19

1999-03-09

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438250, 438253, 438393, 438396, H01L 218242

Patent

active

058799818

ABSTRACT:
A semiconductor memory device including memory cells with the stacked-capacitor structure that makes it possible to prevent a contact pad from being damaged. This device includes a memory cell area and a peripheral circuit area formed on a semiconductor substrate. An interlayer insulating layer having first and second penetrating holes is formed to cover the entire substrate. A capacitor has lower and upper electrode and a dielectric located between these electrodes. The lower electrode is electrically connected to the first element through the first penetrating hole. Each of the peripheral circuits has a second element, a contact pad electrically connected to the second element, a pad insulating layer formed to cover the contact pad, a pad protection layer formed on the pad insulating layer, and an interconnection conductor electrically connected to the contact pad through a contact hole penetrating the pad protection and pad insulating layers. The contact pad is electrically connected to the second element through the second penetrating hole. The lower electrode and the contact pad are made by using a same conductive layer. The dielectric and the pad insulating layer are made by using a same insulative layer. The upper electrode and the pad protection layer are made by using a same conductive layer.

REFERENCES:
patent: 5352623 (1994-10-01), Kamiyama
patent: 5405800 (1995-04-01), Ogawa et al.
patent: 5432732 (1995-07-01), Ohmi
patent: 5608248 (1997-03-01), Ohno
patent: 5612241 (1997-03-01), Arima
patent: 5631182 (1997-05-01), Suwanai et al.
T. Tokuyama et al., "MOS LSI Fabrication Technology", published by Nikkel McGraw-Hill Inc., 1885, pp. 177-178.
IEDM 94, Technical Digest, pp. 927-929, "A 0.29-.mu.m.sup.2 MIM-Crown Cell and Process Technologies for 1-Gigabit Drams", published 1994.

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