Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-04-07
2000-07-25
Fourson, George
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438433, 438450, H01L 21762
Patent
active
06093591&
ABSTRACT:
In a Bi-CMOS integrated circuit device, to reduce a collector-substrate junction capacitance in an NPN transistor and to reduce the step of forming an anti-punch-through layer of the N-channel MOS transistor. Using as a mask a resist pattern having windows made on an element isolation LOCOS film 113a, 113c and P-type well layer 106, impurities are ion-implanted to form a channel stopper layer 115a, 115b for element isolation of a NPN transistor and an anti-punch-through layer 115c for a N-channel MOS transistor. Thus, a sufficient element isolation withstand voltage can be assured while avoiding an increase in the collector-substrate capacitance of the NPN transistor which is due to the transverse diffusion of the channel stopper layer when an epitaxial layer, well layer and LOCOS film are formed. In addition, without increasing the number of steps, the drain-source withstand voltage of the N-channel type MOS transistor and the short channel durability can be improved.
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Fourson George
Matsushita Electronics Corporation
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