Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-28
2001-07-24
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S592000, C438S305000
Reexamination Certificate
active
06265272
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of semiconductor device fabricating process, and more particularly to a method of fabricating a metal-oxide semiconductor (MOS) device suitable for using in the deep sub-micron process. The produced MOS device has elevated source/drain regions. Later, when performing a self-aligned silicidization process, the elevated source/drain regions are reacted to form a metal silicide. This can prevent ultra-shallow junction structure damage and thus improve product yield.
2. Description of Related Art
With the continuous progress in semiconductor manufacture technology, process precision has come into a so-called deep sub-micron era. In the deep sub-micron process, many device coefficients (such as the line width) are much smaller than that in prior art devices. Although utilizing electrical devices with smaller size provides the advantage of high integration, the manufacturing process itself is more difficult than ever. This invention is intended for a MOS transistor with shallow junction structure and provides a novel solution for preventing the shallow junction damage of a miniature device when performing a self-aligned silicidization process.
A shallow junction structure is mainly used in the source/drain regions of a MOS device. By forming shallow junction source/drain doped regions, lateral diffusion can be prevented and thus the properties of the MOS device are improved. As the process resolution increases, the source/drain regions of a MOS device are becoming even shallower. After completing the fabrication of a MOS device (wherein the gate electrode as well as the source/drain regions are fabricated), a self-aligned silicidization process is performed to form a metal silicide layer on the gate electrode and the source/drain regions, thus improving the junction characteristics between the device electrodes and the interconnects (i.e., reducing the contact resistivity). Such a self-aligned silicidization process, however, would probably cause the problem of shallow junction damage if a deep sub-micron process were conducted.
In a conventional self-aligned silicidization process, a metal layer, such as a titanium (Ti) layer, is sputtered on the device. By providing a high temperature, the metal layer is reacted with the silicon ingredient to form a metal silicide layer (e.g. titanium silicide, TiSi
x
). The un-reacted portion of the metal layer, such as that over the sidewall spacer of a gate electrode, is then removed. Thus, the desired metal silicide structure is achieved. As has been described above, not only the sputtered metal layer but also the silicon layers of the device are needed to execute the silicidization process. That is, a certain amount of silicon in the device is lost in the self-aligned silicidization process. For a shallow junction MOS device, it would consume too much intrinsic silicon in the source/drain regions and then cause damage to the shallow junction structure.
Regarding the above problem, most of the solutions currently in use intend to provide an additional silicon ingredient for the self-aligned silicidization process, thereby preventing the consumption of too much silicon in the source/drain regions. For example, after forming the electrodes of the semiconductor device (such as the gate electrode and the source/drain regions), a silicon implantation process is performed to provide additional silicon on the source/drain regions, or a selective epitaxial process is conducted to deposit additional silicon on the source/drain regions. Therefore, this additional silicon ingredient can be used to react with a metal layer to form the metal silicide layer without having to consume the intrinsic silicon of the source/drain regions.
However, since the solutions currently used are performed after finishing the semiconductor device fabrication, several problems occur. For example, the silicon implantation process not only adds the silicon ingredient to the source/drain regions, but also adds the silicon ingredient to other undesired areas, such as the sidewall spacer of the gate electrode. That is, the presence of the silicon ingredient outside the source/drain regions could cause a reaction with the metal layer to form a metal silicide layer, resulting in a short circuit problem. On the other hand, although the selective epitaxial process is able to form a silicon layer onto the desired area, a relatively high temperature of about 800° C. to 1100° C. is required. This would therefore raise the production cost and reduce the manufacturing efficiency.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of fabricating a semiconductor, capable of solving the shallow junction damage problem when forming the self-aligned metal silicide layer, wherein no short circuit problem occurs and no high temperature treatment is needed.
In accordance with the object of the present invention, a fabrication process for forming a semiconductor device with elevated source/drain regions on a substrate is disclosed. Before forming the semiconductor device, an elevated silicon layer is provided on portions of the substrate that will form the source/drain regions. The elevated silicon layer is isolated from a portion of the substrate that will form a gate electrode. Hence, a sidewall spacer can be formed therebetween, and the problem of a short circuit between the gate electrode and source/drain regions can be prevented.
Next, a gate dielectric layer and a gate electrode layer are successively formed on the elevated silicon layer. By using an appropriate etching process, a gate structure is fabricated. Thereafter, as in the current MOS device process, a lightly doped ion implantation, a sidewall spacer, and a heavily doped ion implantation are applied accordingly. The elevated silicon layer is then used as a reactant for performing a self-aligned silicidization process. Consequently, even if some silicon ingredient of the silicon substrate is consumed in the silicidization process, there is no apparent influence on the shallow junction structure.
In a preferred embodiment of the present invention, the elevated silicon layer is made of polysilicon. The thickness of the polysilicon layer is varied depending on the amount of sputtered metal layer and the reaction conditions of the silicidization.
According to the present invention, the elevated silicon layer can be formed by the following two methods:
In a first method, a sacrificial dielectric layer is formed on the substrate. A photolithography and etching process is then performed on the sacrificial dielectric layer to form a gate electrode mask on a portion of the substrate that will form a gate electrode. Next, a silicon layer is formed overlying the gate electrode mask and the substrate. The portion of the silicon layer over the gate electrode mask and its adjacent area is then removed, thereby forming an elevated silicon layer for forming the source/drain regions of a semiconductor, device. This can be accomplished either by using a modified gate electrode photomask or by performing a chemical-mechanical polishing (CMP) process. Finally, the gate electrode mask is removed to complete the fabrication of the elevated silicon layer.
In a second method, a silicon layer and a dielectric layer are successively formed on the substrate. Next, by using a gate electrode photomask, a photolithography and etching process is performed to the dielectric layer so as to reveal the silicon layer over a portion of the substrate that will form a gate electrode. A thermal oxidization process is then performed to convert the revealed silicon into a thermal oxide layer. Finally, the thermal oxide layer and the remaining portion of the dielectric layer are removed to complete the fabrication of the elevated silicon layer.
REFERENCES:
patent: 5079180 (1992-01-01), Rodder et al.
patent: 5200352 (1993-04-01), Pfiester
patent: 5677214 (1997-10-01), Hsu
patent: 5798278 (1998-08-01), Chan et al.
patent: 5872039
Booth Richard
Nath & Associates PLLC
Novick Harold L.
Winbond Electronics Corp.
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