Method of fabricating a semiconductor device in which no...

Details Method of fabricating a semiconductor device in which no... Method of fabricating a semiconductor device in which no...

1997-08-15

2003-03-25

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000, C438S305000, C438S210000, C438S241000

Reexamination Certificate

active

06537882

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device, particularly, an MOS type IC and also to a fabrication process thereof.
2. Description of the Related Art
A semiconductor device generally has a regularly arranged area with a markedly high density and a randomly arranged area with a relatively wide pattern width and distance. A semiconductor memory can be given as one typical example of it. The regularly arranged memory cell region of such a semiconductor memory tends to contain a conductor layer which does not exist in the other regions, leading to a large unevenness on the wafer. This unevenness causes various disturbances in the light-exposure etching step which is indispensable for the fabrication of a semiconductor device, thereby forming a barrier to the miniaturization promotion.
One conventional example of an MOS memory will hereinafter be described with reference to the drawings.
FIGS.
2
(
a
) to (
f
) illustrate an MOSDRAM formed on a P-type substrate
201
. They indicate the fabrication process of a transistor structure until its completion with attention being paid to an N-channel type MOSFET in a memory cell region and an N-channel type MOSFET in a peripheral circuit region. There are products having a P-channel type MOSFET or a bipolar device in the peripheral circuit region but here, such products are omitted for the sake of clear technical explanation. Incidentally, it is easy to incorporate such devices on the same semiconductor device. In Japanese Patent Application Laid-Open No. 259400/1993, specifically described is a process for the fabrication of a DRAM having a CMOS circuit in the peripheral circuit region.
On the P-type semiconductor substrate
201
, a thick silicon oxide film is selectively formed as a field insulation layer
202
in an element isolation region by the LOCOS method using a silicon nitride film as an oxidation resistant layer. An appropriate treatment is then given to the active region, whereby a gate insulation layer
203
is formed, for example, to a thickness of 100 Å. All over the surface, a polycrystalline silicon layer
204
which is to be a gate electrode is allowed to grow to a thickness of 2000 Å by the CVD method [FIG.
2
(
a
)]. At this time, a channel stopper highly-concentrated P
+
region, which is not illustrated, is formed in advance directly beneath the field insulation layer
202
.
A photoresist
205
is then formed by the light exposure method, whereby a gate electrode
204
a
is formed. At this time, it is the common practice to carry out simultaneous formation of an N-channel type transistor constituting a memory cell and an N-channel type transistor in the peripheral circuit region [FIG.
2
(
b
)], which is presumed to be conducted in order to avoid an increase in the trend control parameters in the fabrication site. Subsequent to the removal of the photoresist
205
, about 2×10
13
cm
−2
of phosphorus is introduced into the substrate
201
in a self-alignment manner by the ion implantation method with the gate electrode
204
a
and field insulation layer
202
as masks, whereby an n
−
(lightly doped) impurity diffusion layer
206
is formed [FIG.
2
(
c
)].
All over the surface, a silicon oxide film of about 1500 Å, for example, is allowed to grow by the CVD method as an insulation layer
207
for the formation of side walls [FIG.
2
(
d
)].
The insulation layer
207
for the formation of side walls is then etched using an anisotropic etching technique, whereby silicon oxide side walls
207
are formed on both sides of each gate electrode as shown in FIG.
2
(
e
).
The memory cell transistor is then covered with a photoresist
209
by the light-exposure method known to date and about 3×10
15
cm
−2
of As is introduced into the source and drain regions of the N-channel MOSFET in the peripheral circuit region, whereby an n
+
impurity diffusion layer
208
is formed [FIG.
2
(
f
)].
In the above-described manner, an N-channel type MOSFET constituting a memory cell and an N-channel type MOSFET constituting a peripheral circuit are formed. The MOSFET of the peripheral circuit is formed as a so-called LDD transistor having side walls of an oxide film, while that of the memory cell is formed as a single-drain type MOSFET constituted by an n
−
impurity diffusion layer.
Through a memory-cell-structure formation step subsequent to the above steps, a memory cell portion having the structure as shown in
FIG. 3
is completed. In
FIG. 3
, indicated at the numerals
301
,
302
,
304
,
306
,
307
and
310
are a P-type semiconductor substrate, a field insulation layer, a gate electrode (word line), an n
−
impurity diffusion layer, a side wall and an n
+
impurity diffusion layer, respectively.
At the opening portions formed on the intrastratum insulation layer on the n
−
source and drain regions of the memory cell transistor formed in the step as shown in FIG.
2
(
f
), polycrystalline silicon plugs
311
and
313
are formed and one of them is connected with a tungsten silicide interconnection
312
which is to be a bit line and the other one is connected with a polycrystalline silicon electrode
314
which is to be one electrode of a memory cell capacitor.
In addition, on the surface of the polycrystalline silicon electrode
314
, a capacitive insulation layer
315
composed of a silicon oxide film and a silicon nitride film is formed, over which a capacitive polycrystalline silicon electrode
316
is formed as the other electrode of the memory cell capacitor, whereby a memory cell is completed. As needed, an intrastratum insulation layer, contact opening, metal interconnection layer are formed in this order by the method known to date, followed by the formation of a passivation layer, whereby the final structure is completed.
FIG. 4
is an equivalent circuit corresponding to the structure illustrated in FIG.
3
. The N-channel type MOSFET constituting a memory cell is formed as a single drain type MOSFET constituted by an n impurity diffusion layer presumably because of the following three reasons: (1) to avoid the influence of crystal defects appearing as a result of the high-concentration ion implantation, (2) to avoid an increase in the leakage current occurring in the region where the heavily-doped impurity diffusion layer is in contact with the channel stopper impurity diffusion layer, and (3) to avoid an increase in the leakage current caused by a punch through between contiguous cells. It becomes very important to satisfy the above three points with the progress of the miniaturization.
Thus, the description has so far been made of, focusing on the process for the fabrication of MOSDRAM. Such a method is however accompanied with the problems because a difference in the density of the patterns between the memory cell region and the peripheral circuit region becomes large and at the same time, the miniaturization in the memory cell region has been drastically accelerated.
In a 64 MDRAM, for example, the gate pitch at the memory cell region reaches about 0.8 &mgr;m, while that at the peripheral circuit region remains only 2 to 3 &mgr;m. Also in the element isolation region, the memory cell region is formed of maximum density patterns of about 0.3 &mgr;m, while the peripheral circuit region is an assembly of rectangles as large as about several tens &mgr;m.
In the first place, a serious problem in the light exposure method has been actualized under such situations. Described specifically, it has come to be difficult to conduct size control in the memory cell region and peripheral circuit region, particularly when the size of the memory cell approaches to the resolution limit.
The size control is difficult in both the field formation step and gate formation step and that in the gate formation step is particularly difficult because of the influence of the denseness or sparseness of the underlayer. This is presumed to be caused mainly

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