Method of fabricating a semiconductor device having triple well

Details Method of fabricating a semiconductor device having triple well Method of fabricating a semiconductor device having triple well

1999-03-08

2000-03-14

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438218, 257269, 257339, 257376, H01L 2976, H01L 2994

Patent

active

060372036

ABSTRACT:
The present invention discloses a semiconductor device having a triple well structure. The semiconductor device includes a N-type impurity doped buried layer, formed in the semiconductor substrate at a predetermined depth from the surface of the first active region; a first P-type well region formed beneath the second active region which is adjacent to the first active region; a second P-type well region formed in the semiconductor substrate to a depth from the surface of the first active region; a first N-type well region formed beneath the third active region; a second N-type well region formed beneath selected portion of the isolation film defining first active region and the second active region; and a first P-type doping region and a second N-type doping region formed respectively right beneath the surface of the first active region and right beneath the surface of the second active region, wherein the dopant concentration of the first doping region is lower than that of the second doping region.

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patent: 5548143 (1996-08-01), Lee
patent: 5554883 (1996-09-01), Kuroi
patent: 5739572 (1998-04-01), Noguchi

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