Method of fabricating a semiconductor device having a multi-laye

Details Method of fabricating a semiconductor device having a multi-laye Method of fabricating a semiconductor device having a multi-laye

1998-03-25

2000-06-27

Whitehead, Jr., Carl

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438623, 438625, 438758, 438760, 438763, 438926, H01L 214763

Patent

active

060806524

ABSTRACT:
A method of fabricating a semiconductor device having a multi-layered wiring and including dummy wiring not contributing to connection of circuit elements, comprising the steps of: a) preliminarily preparing relationship between width of an isolated lower level wiring and thickness of an interlayer insulating layer with a planarized function formed on the isolated lower level wiring; b) preparing experimental results by forming dense wiring patterns in a first region on a semiconductor substrate, forming an interlayer insulating layer with a planarized function thereon, and measuring thickness of the interlayer insulating layer; c) determining a width of a dummy wiring to be disposed below an isolated upper level wiring, based on the relationship and the measuremental result; d) forming dense lower level wirings in a first region on another semiconductor substrate and a single lower level wiring having the desired width as a dummy wiring only at a location where an upper level wiring is to be formed in a second region on another semiconductor substrate, where an isolated wiring is to be formed as an upper level wiring; e) forming an interlayer insulating layer with a planarizing function to cover the lower level wirings; and f) forming an upper level wirings on the interlayer insulating layer in the first and second regions. A semiconductor device with a multi-layered wiring can be manufactured using a small quantity of data and has upper level wirings on the surfaces of a substantially same level.

REFERENCES:
patent: 4916514 (1990-04-01), Nowak
patent: 4984060 (1991-01-01), Ohmi et al.
patent: 5032890 (1991-07-01), Ushiku et al.
patent: 5488007 (1996-01-01), Kim et al.
patent: 5639697 (1997-06-01), Weling et al.
patent: 5652465 (1997-07-01), Hosoda et al.
patent: 5825712 (1998-10-01), Higashi et al.
patent: 5894170 (1999-04-01), Ishikawa
patent: 5998303 (1999-12-01), Sato

Affiliated with

Also associated with

Rating

Method of fabricating a semiconductor device having a multi-laye does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a semiconductor device having a multi-laye, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a semiconductor device having a multi-laye will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1784140