Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-03
2002-11-19
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S301000
Reexamination Certificate
active
06482705
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION(S)
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
REFERENCE TO A MICROFICHE APPENDIX
Not Applicable
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to metal oxide semiconductor field effect transistors (MOSFETs) in semiconductor devices. Even more particularly, the present invention relates to semiconductor devices having MOSFETs incorporating silicon-germanium (SiGe) structures.
2. Description of the Background Art
Currently, high dielectric constant (high-k) materials used for gates permit further reduction of gate equivalent oxide thickness (EOT) without significant tunneling leakage current as would, otherwise, occur in a conventional gate using silicon dioxide (SiO
2
) as a gate oxide. However, most high-k materials will react with a silicon substrate in a temperature range of ≧750° C. Thus, the semiconductor industry has an ongoing interest in improving the post-gate-fabrication process. A conventional related art gate electrode is formed from polysilicon (poly-Si) and has several disadvantages: (1) a non-adjustable work function that is unsuitable for threshold voltage design of a MOSFET being formed on a thin-film fully-depleted undoped-channel, (2) a low dopant activation rate, (3) an inferior suppression of boron (B) diffusion in a p
+
-type gate. Related art raised source/drain (r-c-S/D) structures are formed by epitaxial techniques and have the following disadvantages: (1) a high deep S/D junction series resistance, and (2) insufficient space for forming a thick silicidation, thereby maintaining a high S/D series resistance. Further, the conventional poly-Si epitaxial technique involves high temperature processing in a range of 1100° C. to 1200° C., which introduces additional and undue thermal budget to the MOSFET. This condition is not preferred in terms of the formation of a steep retrograde well and an ultra-shallow S/D extension junction. Therefore, a need is seen to exist for a method of fabricating a semiconductor device, having a MOSFET incorporating an alternative structure for preventing reaction with an underlying silicon substrate, and a device thereby formed.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention provides a method of fabricating a semiconductor device, having a MOSFET incorporating a distinct structure for preventing reaction with an underlying silicon substrate, as well as a device thereby formed. The present invention device comprises a MOSFET having an amorphous-silicon-germanium (&agr;-SiGe) gate electrode and an elevated crystalline silicon-germanium (c-SiGe) source/drain structure. An &agr;-SiGe gate electrode has several advantages over the related art polysilicon (poly-Si) gate electrodes: (1) an adjustable work function that is suitable for threshold voltage design for a MOSFET being formed on a thin-film fully-depleted undoped-channel MOSFET, (2) a higher dopant activation rate, (3) a superior suppression of boron (B) diffusion (i.e., penetration) in a p
+
-type gate. A gate electrode formed from &agr;-SiGe also streamlines the fabrication process in that the present invention &agr;-SiGe material requires simple processing, in contrast to related art refractory metal gates electrodes. A raised c-SiGe source/drain (r-c-S/D) structure is extremely useful in ultra-large scale integration (ULSI) MOSFETs as it provides the following advantages: (1) a reduced deep S/D junction series resistance, and (2) more space for a thicker silicidation, thereby reducing S/D series resistance.
By way of example, and not of limitation, a semiconductor device, having a MOSFET with an amorphous-silicon-germanium (&agr;-SiGe) gate electrode and an elevated crystalline silicon-germanium (c-SiGe) source/drain structure is generally fabricated according to the present invention by simultaneously depositing and polishing an &agr;-SiGe film and subsequently heating the polished &agr;-SiGe film in a temperature range of approximately ≦600° C., preferably in a range of approximately 550° C. to approximately 550° C. Also byway of example, the present invention device may also be fabricated by: (1) depositing an &agr;-SiGe layer; (2) simultaneously forming a raised &agr;-SiGe source/drain structure and a &agr;-SiGe gate electrode by polishing the &agr;-SiGe layer; and (3) annealing the raised &agr;-SiGe source/drain structure and the &agr;-SiGe gate electrode in a temperature range of approximately 550° C. to approximately 600° C. in a heating chamber such as an annealing furnace, and using a technique such as solid-phase epitaxy, thereby forming the &agr;-SiGe gate electrode and the raised c-SiGe source/drain structure.
Advantages of the present invention include, but are not limited to, preventing a high deep S/D junction series resistance and providing sufficient space for forming a thick silicidation as well as an alternative structure for preventing reaction with an underlying silicon substrate. Further advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.
REFERENCES:
patent: 5155571 (1992-10-01), Wang et al.
patent: 5571744 (1996-11-01), Demirlioglu et al.
patent: 5955759 (1999-09-01), Ismail et al.
patent: 6228692 (2001-05-01), Tsutsu
patent: 6319799 (2001-11-01), Ouyang et al.
A. Chatterjee, et. al., CMOS Metal Replacement Gate Transistors Using Tantalum Pentoxide Gate Insulator, IEDM 1998.
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Le Thao
Nelms David
LandOfFree
Method of fabricating a semiconductor device having a MOSFET... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a semiconductor device having a MOSFET..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a semiconductor device having a MOSFET... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2933503