Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-03
2004-02-03
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C438S305000, C438S591000, C438S595000, C257S408000, C257S410000
Reexamination Certificate
active
06686248
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION(S)
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
REFERENCE TO A MICROFICHE APPENDIX
Not Applicable
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to small high density semiconductor devices. More particularly, the present invention relates to forming MOS transistors in semiconductor devices. Even more particularly, the present invention relates to eliminating contamination when using high-k materials during fabrication of a MOS transistor in a semiconductor device.
2. Description of the Background Art
As the critical dimensions of transistors continues to be reduced, the thickness of the gate oxide also requires reduction. Currently, the greatest challenge in the effort to reduce gate oxide thickness, is the elimination of the dramatically increasing direct tunneling leakage current through a very thin gate oxide (i.e., <25 Angstroms). In order to suppress such severe gate current leakage current, a high dielectric constant (high-k) material must be used as a gate dielectric to replace the conventional thermal oxide. Further, this high-k material must have a physical thickness much greater than that of the conventional thermal oxide. The direct current density is exponentially proportional to the dielectric material's physical thickness. Therefore, the direct tunneling current flow through the gate insulator is significantly reduced. This is the major motivation of using a high dielectric constant material as a gate insulator for a very small transistor. A few metal oxides exist, such as titanium dioxide (TiO
2
) and tantalum pentoxide (Ta
2
O
5
), which can be used as a high-k material.
However, one of the greatest problems associated with using high-k materials is the potential contamination occurring during post-gate-processing steps, such as during ion implantation. The sputter-out metal atoms (e.g., Ti and Ta) may cause contamination to the implantation chamber. Therefore, a need exists for a new process using high-k materials without creating potential metal contamination.
BRIEF SUMMARY OF THE INVENTION
Accordingly, the present invention generally provides a method of forming a semiconductor device having a MOS transistor with a high dielectric constant material without metal contamination. In particular, the present invention method comprises forming a protective layer comprising a dielectric capsulate layer on at least one sidewall of a gate stack. The dielectric capsulate layer may be formed from a material such as an oxide.
By way of example, and not of limitation, a semiconductor device having a MOS transistor with a high dielectric constant material without metal contamination is fabricated in accordance with the present invention by: (a) forming a gate stack, comprising a high dielectric constant material layer, such as TiO
2
and Ta
2
O
5
, on a semiconductor substrate; (b) forming a gate electrode, such as polysilicon, on the high dielectric constant material layer; (c) depositing a low dielectric constant material (low-k) layer, such as silicon dioxide (SiO
2
), preferably having a thickness in a range of approximately 150 Angstroms to approximately 250 Angstroms on the gate
20
and on at least one exposed portion of the substrate; (d) etching the low dielectric constant material layer, thereby forming a dielectric capsulate layer on at least one sidewall of the gate stack; (e) forming a pair of shallow source/drain extensions (S-S/D-E) in a first region of the substrate, preferably by implanting a plurality of first dopant ions at a tilt angle &thgr; with a horizontal offset w defined by a thickness of the dielectric capsulate layer; (f) forming at least one spacer comprising a thin liner, such as silicon dioxide (SiO
2
), on the low-k layer and on a portion of the substrate; (g) forming a spacer material, such as silicon nitride (Si
3
N
4
), on the thin liner; (h) forming a pair of deep source/drain contact junctions (D-S/D-J) in a second region of the substrate below the first region, by vertically implanting a plurality of second dopant ions at an approximately zero degree tilt angle with a horizontal offset d defined by a thickness of the at least one spacer; and (I) completing fabrication of the semiconductor device.
Advantages of the present invention include providing a method for using high-k materials to suppress severe gate current leakage current and a method for using high-k materials without creating metal contamination. Further advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without thereon placing limitations.
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Advanced Micro Devices , Inc.
Farjami & Farjami LLP
Wilson Christian D.
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