Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2006-02-28
2006-02-28
Pert, Evan (Department: 2826)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S761000
Reexamination Certificate
active
07005367
ABSTRACT:
A method of fabricating a semiconductor device that includes dual spacers is provided. A nitrogen atmosphere may be created and maintained in a reaction chamber by supplying a nitrogen source gas. A silicon source gas and an oxygen source gas may then be supplied to the reaction chamber to deposit a silicon oxide layer on a semiconductor substrate, which may include a conductive material layer. A silicon nitride layer may then be formed on the silicon oxide layer by performing a general CVD process. Next, the silicon nitride layer may be etched until the silicon oxide layer is exposed. Because of the difference in etching selectivity between silicon nitride and silicon oxide, portions of the silicon nitride layer may remain on sidewalls of the conductive material layer. As a result, dual spacers formed of a silicon oxide layer and a silicon nitride layer may be formed on the sidewalls.
REFERENCES:
patent: 6077791 (2000-06-01), DeTar
patent: 6218314 (2001-04-01), Lin
patent: 2000-40109 (2000-07-01), None
S.C. Song et al., “Ultra Thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N20 oxidation of NH3-nitrided Si”, 1999, Symposium on VLSI Technology Digest of technical Papers, pp. 137-138.
Korean Office Action, Notice to Submit Response, dated Aug. 16, 2004.
Heo Seong-Jun
Ku Ja-Hum
Lee Chang-Won
Sun Min-Chul
Youn Sun-Pil
Harness Dickey & Pierce
Pert Evan
Samsung Electronics Co,. Ltd.
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