Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-28
2003-05-27
Hu, Shouxiang (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S527000, C438S682000, C438S683000
Reexamination Certificate
active
06569743
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and in particular, to a semiconductor device fabrication method that ensures reliable silicidation on a narrow active region.
2. Description of the Related Art
As semiconductor devices develop toward high integration, high performance, and low voltage operation, a low-resistance gate material is required to reduce the gate length of a transistor and a memory cell through the formation of fine patterns and to improve the device's characteristics. The thickness of a gate insulating layer must in turn become smaller to increase a channel current in a transistor and a memory cell for low voltage operation. Furthermore, in order to prevent short channel effects caused by the decrease in the gate length of a transistor and to ensure a margin against punch-through, the junction depth of the source/drain regions should be reduced and the parasitic resistance, that is, the surface resistance and the contact resistance of the source/drain regions should be reduced.
Under these circumstances, studies have been conducted on a self-aligned silicide (salicide) process to reduce the resistivity of a gate and the sheet and contact resistance of source/drain regions. This self-aligned silicide process operates by forming a silicide layer on the surfaces of the gate and the source/drain regions. The salicide process refers to the selective formation of a silicide layer such as a titanium silicide (TiSiX) layer on a gate electrode and source/drain regions.
FIG. 1
is a vertical sectional view of an N-channel MOS (Metal Oxide Semiconductor) transistor fabricated by a conventional salicide process. As shown in
FIG. 1
, a gate insulating layer
12
is grown by performing a thermal oxidation on the surface of a silicon substrate
10
that has an active region on it, defined by a field oxide film (not shown). A conductive layer such as a polysilicon is then deposited for use as a gate, on the gate insulating layer
12
by CVD (Chemical Vapor Deposition). The polysilicon layer is then doped to be of an N-type by ion implantation and is then patterned into a gate
14
by photolithography.
Subsequently, N
−
active regions
16
are formed as lightly doped drain (LDD) regions on the surface of the substrate
10
at opposite sides of the gate
14
by ion-implanting an N-type dopant. In particular, phosphorous (P) may be used at a low dose (e.g., at a dose of 1×10
13
−9×10
14
ions/cm
2
) with the gate
14
being used as an ion-implanting mask.
Spacers
18
are then formed on the sidewalls of the gate
14
by depositing an insulating layer on the resultant structure, including the N
−
active regions
16
, and then etching back the insulating layer by anisotropical etching such as RIE (Reactive Ion Etching). Here, the insulating layer is formed of a silicidation blocking material, such as a nitride or an oxide. Then, N
+
active regions
20
are formed as high-concentration source/drain regions on the surface of the substrate
10
at opposite sides of the spacers
18
by ion-implanting an N-type dopant. In particular, arsenic (As) may be used at a high dose (e.g., at or above a dose of 1×10
15
ions/cm
2
) with the spacers
18
and the gate
14
being used as an ion-implanting mask.
Afterwards, a silicide forming metal material, such as titanium (Ti) is deposited on the resultant structure, including the N
+
active regions
20
, and the titanium is subjected to rapid thermal annealing (RTA) or thermal treatment using a furnace so that silicidation takes place in an area where the titanium contacts silicon. As a result, a titanium silicide (TiSi
2
) layer is formed on the surfaces of the exposed N
−
and N
+
active regions
16
and
20
and on the gate
14
. Then, an unreacted titanium layer is selectively removed, using an etchant which does not damage the silicide layer
22
, the silicon substrate
10
, or the gate insulating layer
12
.
A problem with the conventional method is incomplete silicidation on the surface of a narrow active region (see “A” of FIG.
1
). This is believed to be caused by the impurity concentration in the silicon substrate
10
. In other words, with the ion-implantation on the silicon substrate
10
at or above a dose of 1×10
15
ions/cm
2
, impurities contained in the silicon in excess of their solid solubility limit are segregated or piled up at the titanium/silicon interface, thereby blocking the diffusion of silicon. This phenomenon is observed to be more serious with arsenic than with phosphorous.
As a result, the diffusion of silicon is more difficult in the narrow region A of
FIG. 1
between gates
14
, than in the remainder of the device. This can lead to incomplete silicidation as compared to a wide region or an increased sheet resistance. For example, when the source region of a transistor, coupled to a common source terminal (V
ss
) of memory cells, is narrow, silicon of a substrate is not sufficiently diffused in the narrow region during the step of forming a titanium silicide layer. As a result, the sheet resistance from the source region to a V
ss
pattern may increase. In a worse case situation, no silicide layer may be formed at all, thereby reducing a voltage margin in a low-voltage operation area of a device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device fabricating method which can minimize or prevent unreliable silicidation on a narrow active region.
To achieve the above object, there is provided a method of fabricating a semiconductor device. In the method, a plurality of gate insulating layers and a plurality of gates are sequentially formed on a semiconductor substrate of a first conductivity type. A first active region of a second conductivity type is then formed in the semiconductor substrate by ion-implanting a first impurity of the second conductivity type at a first dose, using the plurality of gates as a mask. Sidewall spacers are then formed of an insulating material on the sidewalls of the plurality of gates. A second active region of the second conductivity type in the semiconductor substrate by masking a narrow portion of the first active region between at least two of the plurality of gates and ion-implanting a second impurity of the second conductivity type at a second dose higher than the first dose. A first silicide layer is then formed over exposed portions of the first and second active regions.
Preferably, the first dose is 1×10
13
ions/cm
2
or higher, and the second dose is 1×10
15
ions/cm
2
or higher.
Preferably, the step of forming a first silicide layer comprises the substeps of: depositing a first metal layer over the exposed portions of the first and second active regions, and thermally treating the first metal layer to form the first silicide layer.
Preferably, the step of sequentially forming a plurality of gate insulating layers and a plurality of gates further comprises the substeps of: forming a first insulating layer over the semiconductor substrate, forming a conductive layer over the first insulating layer, and patterning the first insulating layer and the conductive layer to form the plurality of gate insulating layers and the plurality of gates, respectively.
The method for fabricating a semiconductor device may further comprise the step of forming a second silicide layer over the plurality of gates. The step of forming the second silicide layer may itself comprise the substeps of: depositing a second metal layer over the plurality of gates, and thermally treating the second metal layer to form the second silicide layer.
According to another aspect of the present invention, another method of fabricating a semiconductor device is provided. In this method, a plurality of gate insulating layers and a plurality of gates are sequentially formed over a semiconductor substrate of a first conductivity type. A first active region of a second conductivity type is t
Kim Han-Soo
Park Yong
Hu Shouxiang
Volentine & Francos, PLLC
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