Method of fabricating a semiconductor device

Details Method of fabricating a semiconductor device Method of fabricating a semiconductor device

2001-01-18

2002-09-03

Chaudhuri, Olik (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S275000, C438S296000, C438S396000

Reexamination Certificate

active

06444515

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating a semiconductor device. In particular, the present invention relates to a semiconductor device and a fabrication method thereof employing a nitride stopper method applied to memory cells such as a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory).
2. Description of the Background Art
A semiconductor device which employs the so called nitride stopper method using a nitride layer as a stopper layer has been known.
FIG. 19
shows one example of a conventional semiconductor device employing the nitride stopper method.
Referring to
FIG. 19
, on a main surface of a silicon substrate
1
, a pair of gate electrodes
2
is formed with a gate insulating layer interposed. Gate electrode
2
has, for example, a doped polysilicon layer
2
a
and a WSi layer
2
b.
A hard mask insulating layer
3
formed of SiO
2
or the like is formed on gate electrode
2
. A thin SiO
2
layer
4
is formed to cover hard mask insulating layer
3
and gate electrode
2
. An SiO
2
sidewall spacer
15
is formed to cover side surfaces of gate electrode
2
and hard mask insulating layer
3
with the thin SiO
2
covering layer
4
interposed.
An SiN stopper layer
5
is formed to cover hard mask insulating layer
3
and SiO
2
sidewall spacer
15
. An interlayer insulating layer
6
formed of SiO
2
or the like is formed to cover SiN stopper layer
5
. A contact hole
7
is formed such that contact hole
7
penetrates interlayer insulating layer
4
, SiN stopper layer
5
and thin SiO
2
layer
6
to reach the main surface of silicon substrate
1
. Contact hole
7
is provided to reach one SiO
2
sidewall spacer
15
, and an SiN sidewall spacer
8
a
is left on the surface of the one SiO
2
sidewall spacer
15
.
An interconnection layer
9
is formed to extend from the inside of contact hole
7
onto interlayer insulating layer
6
. Interconnection layer
9
includes a doped polysilicon layer
9
a
and a WSi layer
9
b
formed thereon.
An isolation width W
4
is defined by the combines thickness of the one SiO
2
sidewall spacer
15
and that of SiN sidewall spacer
8
a
formed on the surface of spacer
15
. Insulation between gate electrode
2
and interconnection layer
9
can be obtained by setting a value of separation width W
4
at a prescribed value or more. In the case of
FIG. 19
, for example, if a width W
1
between electrodes adjacent to each other is 0.24 &mgr;m, tan opening width W
2
of the bottom of contact hole
7
is approximately 0.06 &mgr;m.
Referring to
FIGS. 20-22
next, a method of fabricating the semiconductor device shown in
FIG. 19
is described.
FIGS. 20-22
are cross sectional views showing the first to the third steps of a fabrication process of the semiconductor device shown in FIG.
19
.
First with reference to
FIG. 20
, gate electrode
2
and hard mask insulating layer
3
are formed on the main surface of silicon substrate
1
with a gate insulating layer interposed, and thin SiO
2
layer
4
is formed to cover these by CVD (Chemical Vapor Deposition) or the like. A silicon oxide layer is deposited on thin SiO
2
layer
4
by CVD or the like, and an anisotropic etching process is applied to the silicon oxide layer. SiO
2
sidewall spacer
15
is thus formed. Etching of SiO
2
sidewall spacer
15
uses plasma. Therefore, plasma is applied to the main surface of silicon substrate
1
.
SiN stopper layer
5
is formed to cover SiO
2
sidewall spacer
15
and hard mask insulating layer
3
by the CVD or the like. Interlayer insulating layer
6
formed of SiO
2
or the like is formed on SiN stopper layer
5
by CVD or the like. A resist
10
patterned into a prescribed shape is provided on interlayer insulating layer
6
.
Next with reference to
FIG. 21
, interlayer insulating layer
6
is selectively etched using resist
10
as a mask. The etching is stopped by SiN stopper layer
5
and an opening
7
a
is formed.
SiN stopper layer
5
is next etched. As a result, contact hole
7
which selectively exposes the main surface of silicon substrate
1
is formed as shown in FIG.
22
. An over etching process is applied to SiN stopper layer
5
so that SiN sidewall spacer
8
a
having a small thickness is left on the surface of SiO
2
sidewall spacer
15
as shown in FIG.
22
.
Interconnection layer
9
is thereafter formed to extend from the inside of contact hole
7
onto interlayer insulating layer
6
by CVD or the like. Accordingly, the semiconductor device shown in
FIG. 19
is obtained through the processes described above.
Because of the plasma applied to the main surface of silicon substrate
1
exposed while SiO
2
sidewall spacer
15
is formed, a problem as described below arises.
Although not shown in
FIG. 19
, an element isolation oxide layer is formed to surround an element formation region where an MOS transistor or the like including gate electrode
2
is formed. Stress generated when the element isolation oxide layer is formed tends to remain in the vicinity of the periphery of the element isolation oxide layer.
SiO
2
sidewall spacer
15
is generally extended over the element isolation oxide layer, and a pn junction may be formed about the periphery of the element isolation oxide layer where the stress remains. In this case, the plasma is applied to the portion where the pn junction is formed. Therefore, leakage current could be easily generated at the pn junction portion. The generated leakage current deteriorates the refresh characteristic of a capacitor if the semiconductor device is a DRAM.
In addition, the opening width W
2
of the bottom of contact hole
7
becomes as small as approximately 0.06 &mgr;m by forming SiO
2
sidewall spacer
15
as shown in FIG.
19
and as described above. As a result, the area of the opening at the bottom of contact hole
7
is decreased.
SUMMARY OF THE INVENTION
The present invention is made to solve the problems described above. An object of the invention is to provide a semiconductor device and a fabrication method thereof by which generation of leakage current resulting from the plasma applied to the main surface of the semiconductor substrate can be restricted, and the area of the opening at the bottom of the contact hole can be increased without increasing the spacing between gate electrodes.
A semiconductor device according to the present invention includes a gate electrode, a hard mask insulating layer, a thin insulating layer, a nitride stopper layer, a sidewall nitride layer, an interlayer insulating layer, and an interconnection layer. The gate electrode is formed on a main surface of a semiconductor substrate. The hard mask insulating layer is formed on a top surface of the gate electrode. The thin insulating layer is formed to cover a side surface of the gate electrode and the hard mask insulating layer. The thin insulating layer refers to an insulating layer having a thickness of approximately 5-20 nm, for example. The nitride stopper layer is directly formed on the thin insulating layer to extend from a portion on one side surface of the gate electrode onto a top surface of the hard mask insulating layer. The sidewall nitride layer is directly formed on the thin insulating layer to cover the other side surface of the gate electrode. The interlayer insulating layer is formed to cover the nitride stopper layer, and provided with a contact hole formed in a self alignment manner that reaches the main surface of the semiconductor substrate and the sidewall nitride layer. The interconnection layer is formed in the contact hole. The sidewall nitride layer may have its upper end on a side surface of the hard mask insulating layer or may cover the side surface of the hard mask insulating layer and be connected to the nitride stopper layer, provided that the sidewall nitride layer tapers away from the semiconductor substrate.
According to the semiconductor device of the present invention, the nitride stopper layer is directly formed on the thin insulating l

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