Method of fabricating a self-aligned split gate of a flash...

Details Method of fabricating a self-aligned split gate of a flash... Method of fabricating a self-aligned split gate of a flash...

1999-12-21

2001-05-08

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000

Reexamination Certificate

active

06228718

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a flash memory. More particularly, the present invention relates to a method of fabricating a self-aligned split gate of a flash memory.
2. Description of the Related Art
At present, nonvolatile memory is widely used in the whole range of electrical devices. In particular, programmable nonvolatile memory having a flash memory structure such as the erasable programmable read-only memory (EPROM) and the electrically erased programmable read-only memory (EEPROM) has attracted immense interest.
In general, a flash memory comprises two gates, a floating gate for charge storage and a control gate for data accessing. The floating gate is in a floating state without being connected to any electrical circuit and is located between the control gate and a substrate while the control gate is connected to a word line.
An over-erase phenomenon easily occurs when erasing the conventional flash memory, so that verification circuits must necessarily be formed in the periphery region of the substrate on verify the memory cells and further to avoid the over-erase problem. However, the processes for fabricating a flash memory, including the additional steps for the verification circuits is complicated and the cost of the fabricating process is increased. In order to overcome the problems of the conventional flash, a split-gate flash memory is developed.
FIG. 1A-1D
are schematic, cross-sectional views illustrating a method of fabricating a split gate for a flash memory cell according to the prior art method.
Referring to the
FIG. 1A
, a tunneling oxide layer
102
is formed on a substrate
100
. Therefore, a polysilicon layer is formed and patterned to form a floating gate layer
104
. Referring to
FIG. 1B
, a dielectric layer
106
and another conducting layer
108
are formed, and then the conducting layer
108
is patterned by a photolithography process and an etching process to form a control gate layer
108
a of the split-gate of the flash memory cell, as shown in FIG.
1
C. Referring to
FIG. 1D
, with the control gate layer
108
a
and the floating gate layer
104
serving as an implant mask, an ion implantion is performed to implant dopant in the substrate
100
, so that a source
110
and a drain
112
are formed. Thereafter, a part of the dielectric layer
106
and a part of the tunneling oxide layer
102
are removed by a wet etching process, and the dielectric layer
106
a
and the tunneling oxide layer
102
a
under the control gate layer
108
a
are left. Consequently, the split-gate of the flash memory cell is completed.
In the about-mentioned process of fabricating the split-gate of flash memory cell, if misalignment occurs during the process of patterning the polysilicon layer
108
for forming the control gate layer
108
a
, the position of the control gate layer
108
a
is changed.
Since the channel length
120
of the control gate
108
a
profoundly affects the performance of the flash memory cell, it is important to controlling the channel length
120
of the control gate
108
a
in the process. Furthermore, changes in the channel length
120
of the control gate
108
a
affects the erase and the program operations of the split-gate of the flash memory.
Positive charges are injected into the floating gate
104
while erasing the split-gate of the flash memory, so that negative charges correspondingly rise in the floating channel region
130
of the substrate
100
. The rising negative charges are equivalent to a virtual extended structure of the source
110
. If the channel length
120
of the control gate
108
a
is shortened because of misalignment, the over-erase phenomenon easily occurs and the performance margin is reduced. Furthermore, the shortened channel length
120
causes the short channel effect and leads a part of the sub-threshold current into the floating gate
104
, therefore affecting the capacitance of the split-gate of the flash memory.
On the other hand, the floating gate channel region
130
is in an off state after a program operation; the punch-through margin of the split-gate of the flash memory is limited by the distance between the source
110
and the drain
112
and is limited by the junction depth of the source
110
and the drain
112
. Consequently, shortening the channel length
120
of the control gate by misalignment leads to a reduction in the distance between the source
110
and the drain
112
, so that punch-through occurs in the whole region between the source
110
and the drain
112
.
SUMMARY OF THE INVENTION
The present invention is a method of fabricating a self-aligned split gate of the flash memory. Aligned layers are formed on predetermined source regions and predetermined drain regions in advance. Spacers are formed on the sidewalls of the aligned layers. The etching rate of the spacers is different from the etching rates of the aligned layers. Therefore, if misalignment occurs during the patterning process to form a split control gate layer, the spacers remain after the aligned layer is removed. The remaining spacers serve as an implant mask during the implantion for source and drain formation, so that the sources and the drains are formed in the positions of the aligned layers by self-alignment.
A method of fabricating a self-aligned split gate of the flash memory according to the first preferred embodiment of the method according to the present invention is provided. A substrate is provided, and the substrate is sequentially divided into a first drain region, a first control gate channel region, a first floating gate channel region, a source region, a second floating gate channel region, a second control gate channel region, and a second drain region. A tunnelling oxide layer and a first conducting layer are formed sequentially over the substrate. The first conducting layer is patterned to form a first aligned layer, a second aligned layer, and a third aligned layer. The first aligned layer covers a part of the first drain region. The second aligned layer covers the first floating gate channel region, the source region and the second floating gate channel region. The third aligned layer covers a part of the second drain region. Thereafter, spacers are formed on the sidewalls of the first aligned layer, the second aligned layer, and the third aligned layer. A conformal dielectric layer and a second conducting layer are then formed over the substrate. A mask layer is formed on the second conducting layer, which mask layer has a first opening over the first drain region, a second opening over the source region, and a third opening over the second drain region. The second conducting layer exposed by the first, the second, and the third opening is removed, and then the dielectric layer and the first aligned layer, a part of the second aligned layer, and the third aligned layer thereunder are also removed in a self aligned process. The tunnelling oxide layer over the first drain region, the source region, and the second drain region are exposed. A remaining second aligned layer over the first floating gate channel region is used as a first floating gate layer. A remaining second aligned layer over the second floating gate channel region is used as a second floating gate layer. A remaining second conducting layer over the first control gate channel region and the first floating gate channel region is used as a first control gate layer. A remaining second conducting layer over the second control gate channel region and the second floating gate channel region is used as a second control gate layer. A first drain in the first drain region, a source in the source region and a second drain in the second drain region are formed by implantion after the mask layer is removed.
The spacers have an etching rate that is different from an etching rate of the first conducting layer. An etchant that has a high etching selectivity between the spacers and the first conducting layer is used during the process for removing the second conducting lay

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