Method of fabricating a self-aligned silicide MOSFET

Details Method of fabricating a self-aligned silicide MOSFET Method of fabricating a self-aligned silicide MOSFET

1998-04-06

1999-07-06

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438592, 257413, H01L 21336, H01L 214763, H01L 213205

Patent

active

059207833

ABSTRACT:
A method of fabricating a MOSFET device in accordance with the present invention can protect the device from the short channel effect and decrease the resistance of a gate of the device. The fabricating method includes the following steps. A device including a substrate, an oxide layer, a gate and a lightly doped region is provided, wherein the oxide layer is formed on the substrate and the gate is formed on the oxide layer. A conducting layer is formed on the oxide layer, and the conducting layer is etched to form a first spacer. Then, the device is implanted to form a heavily doped region. A dielectric layer is deposited on the device, and the dielectric layer is etched to form a second spacer. The oxide layer is etched to expose part of the side walls of the gate. Then, a self-aligned silicide is further processed to complete the fabricating processes. As a result, the MOSFET device has an ultra-shallow junction under the first spacer to reduce the source/drain resistance and increase the operating rate of the device.

REFERENCES:
patent: 4925807 (1990-05-01), Yoshikawa
patent: 5102815 (1992-04-01), Sanchez
patent: 5583067 (1996-12-01), Sanchez
patent: 5766969 (1998-06-01), Fulford, Jr. et al.
patent: 5770507 (1998-06-01), Chen et al.
patent: 5783475 (1998-07-01), Ramaswami
patent: 5783479 (1998-07-01), Lin et al.

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