Method of fabricating a self-aligned shallow trench isolation

Details Method of fabricating a self-aligned shallow trench isolation Method of fabricating a self-aligned shallow trench isolation

2001-03-01

2003-02-04

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S424000, C438S430000, C438S446000

Reexamination Certificate

active

06514816

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to a semiconductor process. More particularly, the present invention relates to a method of fabricating a self-aligned shallow trench isolation (SASTI).
2. Description of the Related Art
A capacitor is a part of a dynamic random access memory (DRAM) that stores data. In order to decrease data error and memory refresh, the capacity of the capacitor has to be increased to improve the efficiency of the operation. One method of increasing the capacity of the capacitor is to increase the surface area of the capacitor, wherein the steps of this method comprise: forming a deep trench (DT) in a substrate, and forming a DT capacitor in the deep trench. Because the depth of the deep trench is very deep, a surface area of the capacitor is increased.
However, the DT capacitor utilizes the surface area of the substrate, so a shallow trench isolation (STI) is fabricated on the top of the DT capacitor in order to utilize the surface area of the substrate effectively. A conventional method of fabricating a STI is described as below:
Referring to
FIG. 1A
, a p-type substrate
100
is provided first and a pad oxide layer
102
and a mask layer
104
of silicon nitride are formed sequentially on the substrate. Two deep trenches
110
are formed in the p-type of substrate
100
. An n-type doped region
120
is formed in the p-type substrate
100
. An internal electrode
125
of the bottom capacitor and an internal electrode
128
of the top capacitor are formed in the deep trenches
110
. A buried plate
121
and an n-type doped region
120
are formed in the p-type substrate
100
located at the lower part of the deep trenches
110
. The n-type doped region is very thin and is connected to an n-type doped region
120
. The buried plate
121
serves as an external electrode for the DT capacitor. A dielectric layer
123
with a very thin thickness is formed in between the internal electrode
125
of the capacitor and the buried plate
121
. The internal electrode
128
of the top capacitor, the p-type substrate
100
and the n-type doped region
120
have a thick collar
127
for isolation. A top surface of the internal electrode
128
of the top capacitor is lower than the surface of the p-type substrate.
Referring to
FIG. 1A
, an n-type doped polysilicon layer
130
is filled into the deep trench
110
and it covers the top part of the internal electrode
128
of the top capacitor. The top surface of the doped polysilicon
130
is lower than the surface of the p-type substrate
100
. A thermal process is carried out to allow doping ions of the n-type doped polysilicon layer
130
to distribute into the surrounding p-type substrate
100
. A doped region
140
is thus formed.
Referring to FIG.
1
B and
FIG. 1A
, a photoresist layer
156
, which has an opening
158
, is formed on the p-type substrate
100
. The photoresist layer
156
exposes the mask layer
104
located between the two deep trenches
110
and a portion of doped polysilicon layer
130
. The photoresist layer
156
is utilized as a mask to etch away all the parts located in the opening
158
. A trench
160
is formed (shown in FIG.
1
B). A remained doped polysilicon layer
130
and the doped region
140
are utilized as buried S/D
150
.
Referring to
FIG. 1C
, the photoresist layer
156
is removed followed by filling the trench
160
with silicon oxide to form a STI
170
. The mask layer
104
and the pad oxide layer
102
c
are removed, and a gate
179
and S/D regions
180
located at both sides are formed on the p-type substrate
100
. The S/D regions
180
are electrically connected to the internal electrode of the top capacitor
128
by the buried S/D
150
.
FIG. 1B
illustrates a conventional method of defining the trench
160
that is not a self-aligned method. An alignment problem between the internal electrode of the top capacitor
128
and the trench
160
often will occur. The quality of the capacitor will be affected. From
FIG. 1C
, most of the doped polysilicon layer
130
is removed during the formation of the trench
160
. A contact area between the buried S/D
150
and the internal electrode of the top capacitor
128
is very small; thus, the resistance in that region becomes very large and affects the efficiency of the device.
SUMMARY OF THE INVENTION
The present invention provides a method of fabricating a self-aligned shallow trench isolation, suitable for a device of a DT capacitor. A preferred embodiment of the present invention provides a method of solving the alignment problem between an internal electrode of a capacitor and a STI, and the high resistance problem between a S/D region and the internal electrode of the capacitor.
The method of the present invention comprises the following steps. A mask layer, two deep trenches and two internal electrodes of a capacitor are sequentially formed on a substrate. Two conductive layers are used to completely fill the two deep trenches. A portion of the mask layer is removed to expose the conductive layers. Then, two spacers are formed on the exposed sides of the two conductive layers, and two doped regions are formed in a substrate located next to the two conductive layers. A patterned photoresist layer is formed to expose at least the spacers located in between the two deep trenches and mask layer. The photoresist layer and the spacers are utilized as masks to etch away the exposed mask layer and expose a portion of the substrate. The photoresist layer is utilized again as a mask to etch the exposed spacers and a portion of the exposed substrate. Sequentially, a remained portion of the photoresist layer and a portion of the conductive layers are removed. Simultaneously, a remained mask layer is used as a mask to remove a portion of the exposed substrate, and a trench is thus formed. The remained portion of the conductive layers completely cover the two internal electrodes of the capacitor. The remained portion of the conductive layer and the doped regions are utilized as a buried S/D. Finally, a shallow trench isolation is formed in the trench.
The present invention further provides a stack structure for a DT capacitor and a STI. The structure comprises: a substrate comprising two deep trenches, two internal electrodes of a capacitor, two conductive layers and two doped regions and a STI. The two internal electrodes of the capacitor are located in the two deep trenches. The two conductive layers are located on a top of the two deep trenches, and completely cover a top portion of the two internal electrodes of the capacitor. Top surfaces of the conductive layers are lower than a surface of a substrate located outside the two deep trenches, and a surface of a substrate in between the deep trenches is lower than the top surfaces of the conductive layers. A trench is thus formed. The substrate, which is located in between two deep trenches has a side portion and a central portion, and the side portion is higher than the central portion. The two doped regions are next to the substrate of the two conductive layers. The two doped regions and the two conductive layers are utilized as two buried S/D. A doping type of the two doped regions and the two conductive layers is different. The STI is filled into the trench.


REFERENCES:
patent: 6184549 (2001-02-01), Furukawa et al.
patent: 6225158 (2001-05-01), Furukawa et al.
patent: 6281069 (2001-08-01), Wu et al.

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