Method of fabricating a self-aligned non-volatile memory cell

Details Method of fabricating a self-aligned non-volatile memory cell Method of fabricating a self-aligned non-volatile memory cell

2002-09-06

2003-09-23

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S267000, C257S316000, C257S321000

Reexamination Certificate

active

06624029

ABSTRACT:

TECHNICAL FIELD
The invention relates to self-aligned non-volatile memory cells, and more particularly to a self-aligned non-volatile memory cell that has a high capacitive coupling ratio and has a thin and small tunneling oxide region.
BACKGROUND ART
FIG. 1
shows a sectional view of an EEPROM 100 (Electrically Erasable Programmable Read Only Memory) as depicted in FIG. 18 of U.S. Pat. No. 4,833,096 which is assigned to the same assignee as the present invention. With reference to
FIG. 1
of the present application, a deep n-well
23
is formed inside a p-type substrate
40
, and N-channel and memory cell devices are defined. N-channel stops and field oxide are formed around the device areas. Channel stops and field oxide are formed by thermally growing a thin oxide layer, depositing a 1000-2500 Å thick nitride layer and removing the nitride from non-device areas, implanting boron ions around the N-well and N-channel device areas, then driving in the boron and thermally growing oxide in the non-device areas not covered by nitride.
The process continues by implanting a first species of N-type impurity in a portion of the memory cell device area, thermally growing a first oxide layer
59
, defining a window therein over the impurity implant, implanting a second species of N-type impurity into the window hole, and regrowing a thick oxide layer in the window. Next, a 2500-3400 Å thick polycrystalline silicon (“polysilicon”) layer is deposited, and removed with the first oxide layer to form the floating gate
71
. A second oxide layer is thermally grown at a temperature of 1000°-1050° C. which ensures that this second oxide layer has a substantially uniform thickness over both the polysilicon floating gate and the substrate. After adjusting the threshold of any enhancement devices, a second gate layer, of either polysilicon or a polysilicon/silicide sandwich, is deposited and selectively removed with the second oxide layer to define gates
95
and
97
for peripheral devices, as well as a second polysilicon gate
99
that, along with floating gate
71
, forms a memory cell
30
. Sources and drains are then formed using the polysilicon gates of the particular device as a self-aligning mask.
The process concludes by defining a double layer of conductive lines in the following manner. First, a boron/phosphorus-doped silica glass
121
covering is applied, contact holes
123
are etched, and the glass is heated to its flow temperature to round the corners of the contact holes. A first layer of conductive lines
131
is then defined. An insulative intermetal layer
133
is deposited, etched back and redeposited to form a substantially planar surface. Via holes
135
are wet/dry etched and the second layer of conductive lines
137
is then defined. A passivation layer
139
can be deposited over the second metal layer
137
, or for single metal layer devices, over the first metal layer
131
.
EEPROM
100
can program/erase faster if its coupling ratio can be made higher. Coupling ratio of memory cell
30
(and also of EEPROM
100
) is the ratio of a first capacitance (not shown) formed between control gate
99
and floating gate
71
of cell
30
over the sum of the first capacitance and a second capacitance (not shown) formed between floating gate
71
and p-substrate
40
of cell
30
. The first and second capacitances are in series; therefore, when the coupling ratio of memory cell
30
increases, with other factors being the same, the voltage drop between floating gate
71
and p-substrate
40
of cell
30
also increases. As a result, it is easier for electrons to tunnel through thin tunnel oxide layer
59
into floating gate
71
. In other words, programming cell
30
becomes faster.
There are at least two methods to increase the coupling ratio of memory cell
30
. A first method is to increase the first capacitance formed between control gate
99
and floating gate
71
of cell
30
. One way to do this is to increase the overlapping area between control gate
99
and floating gate
71
of cell
30
.
A second method is to decrease the second capacitance formed between floating gate
71
and p-substrate
40
of cell
30
. This can be done by reducing the overlapping area between floating gate
71
and p-substrate
40
of cell
30
. It should be noted that although increasing the thickness of a dedicated tunnel oxide region
59
between floating gate
71
and p-substrate
40
of cell
30
would decrease the second capacitance and hence increase the coupling ratio, that would also make it much harder for electrons to tunnel through the tunnel oxide region
59
. Therefore, as a compromise, the dedicated tunnel oxide layer
59
should be thinner at only a small portion of the tunnel oxide region
130
to serve as a pathway for electrons to tunnel from p-substrate
40
into floating gate
71
and should be thicker at the rest of tunnel oxide region
59
.
However, there is still room for improvement using the second method mentioned above. It is the object of the present invention to improve upon the prior art method of decreasing the second capacitance formed between the floating gate and the p-well or p-substrate, by providing a method of forming a memory cell in which the tunnel oxide region is thinner at a small portion in order to create a pathway for electrons to tunnel into the floating gate, while having the tunnel oxide region remain thicker at other places.
SUMMARY OF THE INVENTION
The non-volatile memory cell of the present invention has a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made narrow; therefore, the thin portion of the oxide layer can also be made small to create a small pathway for electrons to tunnel into the floating gate.


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