Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
1999-05-14
2001-01-30
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S576000, C438S701000, C438S704000, C438S737000, C438S175000
Reexamination Certificate
active
06180440
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods of fabricating field-effect transistors, and more specifically to a method of fabricating a high-power field-effect transistor of a recessed gate structure on a compound semiconductor substrate for use in the microwave region.
2. Description of the Related Art
For high power and microwave applications, recessed gate field-effect transistors are currently used. This type of field-effect transistor has the gate electrode formed in a slot etched in a compound semiconductor substrate, such as GaAs, between the source and drain electrodes. The use of the same mask for etching the slot and depositing metal to form the gate electrode results in the gate metal being placed in the center of the slot. Use of a recessed gate structure has the advantages that the extra channel thickness on each side of the gate reduces parasitic resistances between the gate and the source and drain and that the position of the gate below the substrate surface does not restrict the ability of the gate to modulate the source-drain current under positive gate bias despite the shrinkage of the depletion region that occurs under positive bias. In addition, low noise is another demand which requires small gate length.
According to a prior art method, a silicon dioxide layer is formed on a semi-insulating substrate and then etched to form a small recess, which is then sputtered with metal. However, if this recess opens upwards with an aspect ratio equal to or greater than unity and one side of the opening is smaller than 0.2 micrometers, difficulty arises to completely fill the gate metal into the recess. This results in the filling gate metal having an undesirable “void”, which in turn causes the gate to increase its resistance and weaken its structural integrity,
In order to overcome this problem, one prior-art solution employs a tapered sidewall forming process during the fabrication of a recessed-gate field-effect transistor, as shown in
FIGS. 1A
to
1
D. According to this approach, an AlGaAs layer
2
and a GaAs layer
3
are successively formed on a GaAs substrate
1
, as shown in FIG.
1
A. On the GaAs layer
3
is deposited an oxide layer
4
which is then etched to form a hole
7
. Using the oxide layer
4
as a photoresist, the GaAs layer
3
and AlGaAs layer
2
are isotropically wet-etched to form a recess
8
whose sidewalls slope down from the bottom of layer
4
. An oxide layer
5
is then grown on the layer
4
so that it fills in the recess
8
, leaving a tapered small recess
9
, as illustrated in FIG.
1
B. The upper oxide layer
5
is then dry-etched to create a hole
10
as illustrated in FIG.
1
C. Because of the presence of the tapered recess
9
, the dry etching process results in the hole
10
having a bevelled edge
10
a
. Metal is then sputtered as shown in
FIG. 1D
to form a gate electrode
6
. Selected areas of the oxide layers
4
and
5
are removed by a patterned etching process to allow the subsequent metalization process to form the source and drain electrodes.
However, it is found that when the horizontal aspect ratio of hole
10
becomes equal to or greater than 2, a “void” still occurs in the filling gate metal as indicated by numeral
11
in FIG.
1
D.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of fabricating a recessed-gate field-effect transistor without producing a void in the filling gate metal.
Another object of the present invention is provide a method of fabricating a recessed-gate field-effect transistor which ensures high precision control on the gate length.
According to the present invention, there is provided a method of fabricating a field-effect transistor comprising the steps of forming a masking layer having an opening therein on laminated compound semiconductor layers, removing a portion of the laminated layers using an etching solution acting through the opening and creating a gate-forming recess having sidewalls tapering in a direction away from the masking layer, filling the gate-forming recess with gate metal and forming a gate electrode, and forming a recess around the gate electrode.
REFERENCES:
patent: 3986200 (1976-10-01), Allison
patent: 5023675 (1991-06-01), Ishikawa
patent: 5389574 (1995-02-01), Mizunuma
patent: 5675159 (1997-10-01), Oku et al.
patent: 5796132 (1998-08-01), Nakano et al.
patent: 5888860 (1999-03-01), Kohno
patent: 5994753 (1999-11-01), Nitta
Davis Jamie L.
Jr. Carl Whitehead
NEC Corporation
Scully Scott Murphy & Presser
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