Method of fabricating a non-volatile semiconductor memory

Details Method of fabricating a non-volatile semiconductor memory Method of fabricating a non-volatile semiconductor memory

2008-09-09

2009-06-30

Chambliss, Alonzo (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S315000, C257S390000, C257SE29129, C257SE21422, C257SE21179, C257SE21680

Reexamination Certificate

active

07553728

ABSTRACT:
An non-volatile semiconductor memory having a linear arrangement of a plurality of memory cell transistors, includes: a first semiconductor layer having a first conductivity type; a second semiconductor layer provided on the first semiconductor layer to prevent diffusion of impurities from the first semiconductor layer to regions above the second semiconductor layer; and a third semiconductor layer provided on the second semiconductor layer, including a first source region having a second conductivity type, a first drain regions having the second conductivity type and a first channel region having the second conductivity type for each of the memory cell transistors.

REFERENCES:
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patent: 7120057 (2006-10-01), Umezawa et al.
patent: 2003/0034520 (2003-02-01), Kusunoki
patent: 2004/0166621 (2004-08-01), Forbes
patent: 2007/0128815 (2007-06-01), Iino et al.
patent: 11-163303 (1999-06-01), None
patent: 2000-174241 (2000-06-01), None

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