Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-09-29
1998-12-01
Chang, Joni
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438245, 438388, H01L 218242
Patent
active
058438203
ABSTRACT:
An improved dynamic random access memory (DRAM) cell using a novel buried horizontal trench capacitor was achieved. A capacitor trench is etched in a silicon substrate. A first high-k dielectric layer is formed on the trench surface, and the trench is filled with a first polysilicon layer and polished back. A second high-k dielectric is deposited and patterned over the polySi-filled trench. A P.sup.- epitaxy is grown on the substrate that also grows inward over the trench, while an amorphous silicon layer of decreasing top surface area grows on the dielectric over the trench. A field oxide is formed in the epi surrounding and isolating a device area aligned over the trench capacitor. A node contact hole is etched in the epi/amorphous Si to the capacitor and has an oxide liner on the sidewall. A second polySi is deposited and etched back to form the node contact to the buried trench capacitor. The gate electrode (access transistor) is formed on the epi layer over the capacitor, and adjacent to the node contact which is connected to one of the two FET source/drain (S/D) areas, while the second S/D is connected to a bit line. The surface over the cell, free for the bit line, and the FET over the capacitor reduces the cell size, while the buried horizontal trench capacitor increases capacitance.
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S. Wolf, "Silicon Processing For The VLSI Era" vol. 2, Lattice Press, Sunset Beach, Ca. 1990, p. 605-611.
Ackerman Stephen B.
Chang Joni
Saile George O.
Vanguard International Semiconductor Corporation
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