Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-02
2001-04-17
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S625000, C438S627000, C438S640000, C438S687000, C438S688000
Reexamination Certificate
active
06218283
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a multi-layered wiring system of a semiconductor device. The method reduces defects that occur during formation of the device and thereby improves reliability of the semiconductor device.
2. Description of the Related Art
As submicron technology advances, there is a demand for making ever smaller chips having a finer pattern for the metal wiring system. Therefore, in the fabrication of semiconductor devices, a desperate need has arisen for a multi-layered wiring process which integrates W-plug, Al-flow and chemical mechanical polishing (CMP) processes.
FIGS. 1 through 4
are diagrams illustrating the sequential production procedures of a conventional method of fabricating a multi-layered wiring system of a semiconductor device. The conventional method is described in four sequential steps with reference to the accompanying drawings. For example, the production procedures of a semiconductor device will be described below: wherein a multiple metal wiring system is made in a fine pattern of less than 0.6 &mgr;m, and a via hole (h) is designed for electrically connecting between the metal wires in a fine width of less than 0.5 &mgr;m, thereby resulting in an aspect ratio of over 2.
At the first step, as shown in
FIG. 1
, a first insulation layer
12
of 0.5-2.0 &mgr;m in thickness is formed by means of a CVD process and a heat treatment process on the semiconductor substrate
10
which includes unit elements (not shown) such as a transistor and a capacitor.
The first insulation layer
12
is constructed in a BPSG single layer structure, three deposition layer structure such as PEOX/USG/PE-TEOS, or four deposition layer structure such as PEOX/O3-TEOS/PE-TEOS/PEOX. Alternatively, the uppermost layer of PEOX can be omitted in the case of the four deposition layer structure.
At the second step, as shown in
FIG. 2
, to improve adhesion between layers, a first conductive layer
14
of a Ti/TiN deposition layer structure is positioned on the first insulation layer
12
. A second conductive layer
16
of 5000-8000 Å in thickness is made of aluminum (Al) alloy and is formed on the first conductive layer
14
by means of a sputter deposition process and a heat treatment process. Then, a first anti-reflective layer
18
(ARL) of Ti and TiN is formed by a sputter deposition process on a second conductive layer
16
. The Ti and TiN of the first conductive layer
14
are respectively 200 Å and 700 Å in thickness. The first anti-reflective layer
18
is 200-600 Å in thickness.
At the third step, as shown in
FIG. 3
, a photosensitive layer pattern (not shown) for a restricting metal wiring system is used as a mask for sequentially etching the first anti-reflective layer
18
, the second conductive layer
16
and the first conductive layer
14
. The first metal wire
16
a
has the anti-reflective layer
18
at the upper portion thereof and the first conductive layer
14
at the lower portion thereof. Then, a second insulation layer
20
of 1.0-2.5 &mgr;m in thickness is formed on the first insulation layer
12
and the first metal wire
16
a
by means of a CVD process. Then, a CMP treatment (or an etch back process) is carried out for planarization of the second insulation layer
20
. To expose predetermined portions on the surface of the first metal wire
16
a
, predetermined portions of the second insulation layer
20
are dry-etched to make a via hole (h) therein. In order to remove the polymer component (for example, a multiple polymerized complex of TiFx or AlFx) formed in the course of the dry-etching process, a wet etching process is carried out. The dry-etching of the second insulation layer
20
and the first anti-reflective layer
18
is performed with an etching gas composed of CHF
3
: CF
4
at the ratio of 1:0.4. The wet etching process, for removing the remaining polymer component, is performed using an HNO
3
based solution as the etching liquid (etchant).
At the fourth step, as shown in
FIG. 4
, a sputter etching process is carried out by using a radio frequency bias (hereinafter referred to as RF sputter etch) to remove a natural oxide layer (Al
2
O
3
) grown in the portions exposed on the surface of the first metal wire
16
a
. The RF sputter etching process is performed to etch the oxide layer of about 400 Å in thickness with an RF power of 800 Watts. The amount of the oxide layer to be etched is not the value set with reference to the natural oxide layer grown on the surface of the first metal wire
16
a
, but the value set with reference to the oxide layer (SiO
2
). A barrier metal layer
22
of Ti/TiN is formed inside the via hole (h) and on the first metal wire
16
a
by means of a sputtering apparatus device having a collimator. A conductive layer
24
of tungsten (W) is formed by a CVD process at the front side to fill the via hole (h). A CMP treatment (or, etch back) is carried out on the conductive layer and the barrier metal layer until the surface of the second insulation layer
20
is exposed, thus forming a conductive plug
24
in the via hole (h).
A third conductive layer
26
of Ti is formed on the conductive plug
24
and the second insulation layer
20
to improve adhesion between layers. A fourth conductive layer of Al alloy and a second anti-reflective layer
30
of TiN are sequentially formed on top of the third conductive layer
26
. Then, a photoresist layer pattern (not shown) for restricting the metal wiring system is used as a mask to sequentially etch the second anti-reflective layer
30
, the fourth conductive layer and the third conductive layer
26
, to form second metal wire
28
with anti-reflective layer
30
at the upper portion thereof and the third conductive layer
26
at the lower portion thereof. The second anti-reflective layer
30
is 200-600 Å in thickness.
There are two problems in the aforementioned procedures (i.e., when a via hole (h) of a multi-layered wiring system in a semiconductor device is constructed as shown in FIG.
4
). First, if the wet etching process is performed to remove the polymer component after formation of the via hole (h), some parts of the first metal wire
16
a
can be simultaneously etched along with the polymer component. In other words, the first metal wire
16
a
inside the first anti-reflective layer
18
, positioned below the via hole (h), is also partially etched in the course of the wet etching process. As a result, a concave portion (part I in
FIG. 3
) is formed inside the anti-reflective layer
18
at the edges of the via hole (h). Thus, the via hole (h) has a deformed profile, which leads to a defective connection between the barrier metal layer
22
and the first metal wire
16
a
because the concave portion (I) is not properly filled to form the barrier metal layer
22
.
Secondly, if the concave portion (I) is formed inside the barrier metal layer
18
below the via hole (h) in the course of the wet etching process, it can be difficult to completely remove the polymer component at the concave portion (I), thereby forming a shadow point where the polymer component remains. When these problems occur, the contact resistance increases in the via hole, which thereby lowers the reliability of the semiconductor device.
SUMMARY OF THE INVENTION
The present invention is provided to solve the aforementioned problems, and one feature of the present invention is to provide a method of fabricating a multi-layered wiring system of a semiconductor device by forming an anti-reflective layer in the structure of Ti/TiN deposition layer with a sputter device having a collimator to reduce fabrication defects (for example, a concave portion inside the anti-reflective layer below the via hole, or a deformed portion called the shadow point in the via hole) to improve the reliability of the semiconductor element.
In accordance with one feature of the present invention, a method is provided for construct
Cho Chan-Hyoung
Park Joo-Sung
Bowers Charles
Nguyen Thanh
Samsung Electronics Co,. Ltd.
The Law Offices of Eugene M. Lee P.L.L.C.
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