Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1996-06-11
2001-01-09
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S595000
Reexamination Certificate
active
06171915
ABSTRACT:
BACKGROUND
The present invention relates to a method of fabricating a MOS-type transistor having a LDD (Lightly Doped Drain and Source) structure and more particularly, to a method of fabricating a MOS-type transistor which has a gate electrode made of molybdenum.
FIG. 3
shows the structure of a conventional MOS-type transistor. This transistor is of a LDD structure and has a gate electrode made of molybdenum.
11
denotes a silicon substrate.
12
is a gate insulating layer.
13
is a gate electrode made of molybdenum.
14
a
and
14
b
are a low density diffusion layer and a high density diffusion layer, respectively and serve as a source/drain.
15
are side wall spacers.
In the prior art, the gate electrode
13
and the low density diffusion layer
14
a
(source/drain) overlap each other as shown in FIG.
3
. This prevents high speed operation as the elements become complicated. Where the gate electrode is made of polysilicon, the polysilicon layer is oxidized under heat to form an oxidized layer around the gate electrode. The thickness of this oxidized layer may be adjusted so as to reduce the amount of overlapping. Molybdenum is however subject to sublimation during heat oxidation. It is quite difficult to form such an oxidized layer and thus, control the amount of overlapping between the gate electrode and source/drain in the event that the gate electrode is made of molybdenum.
It is an object of the present invention to provide a method of fabricating a MOS-type transistor having a LDD structure and including a gate electrode made of molybdenum, which can reduce the amount of overlapping between the gate electrode and source/drain.
SUMMARY
The present invention provides a method of fabricating a MOS-type transistor which comprises the steps of forming a first pattern including a gate electrode made of molybdenum, subjecting the first pattern to nitriding process so as to form a second pattern composed of an interior electrode layer and a nitride layer outside of the electrode layer, whereby the nitride layer has a thickness corresponding to the amount of overlapping between the second pattern and source/drain.
REFERENCES:
patent: 4429011 (1984-01-01), Kim et al.
patent: 4471004 (1984-09-01), Kim
patent: 4849377 (1989-07-01), Kim et al.
patent: 5476802 (1995-12-01), Yamazaki et al.
Jordan and Hamburg LLP
Nippon Precision Circuits Inc.
Wilczewski Mary
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