Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-25
2001-10-02
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S212000, C438S221000, C438S224000, C438S289000
Reexamination Certificate
active
06297082
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for fabricating a semiconductor. More particularly, the present invention relates to a fabrication method for a metal oxide semiconductor (MOS) transistor combining a dual threshold voltage process and a local channel implantation.
2. Description of Related Art
Conventionally, in the manufacture of the MOS transistor, a field oxide layer for defining an active region is formed in the substrate. An ion implantation step is then performed so that a well is formed in the active region, and two implantation regions are globally formed for providing a threshold voltage (V
T
) adjustment and an anti-punch through layer respectively. On the substrate, gates are formed with spacers located on sidewalls of the gate. Furthermore, source/drain (S/D) regions having lightly doped drains (LDD) are formed underneath both sides of the gate in the substrate. An implantation region, which provides the anti-punch through layer, is located below the S/D region, wherein a junction capacitance, which affects the efficiency of the device, exists between the implantation region and the S/D region.
As the integration of the device increases with a decrease in the line width, a shallow trench isolation (STI) becomes the necessary isolation structure for the device when the process advances to the technology of below 0.25 micron. However, different outcomes are produced due to the device characteristics if the field oxide layer is substituted with the STI to isolate the device.
It was known that if the field oxide layer serves as a device isolation structure, V
T
of the transistor increases when the length of the gate (i.e. channel length) increases. This is known as a short channel effect (SCE). As the width of the gate increases, V
T
of the transistor reduces as a consequence of a narrow channel effect (NCE). However, if the STI is substituted for device isolation, V
T
of the transistor increases at first and then decreases when the gate width gradually increases. This phenomenon is different from the outcome produced when the field oxide layer is used, and is therefore known as a reverse short channel effect (R-SCE). When the width of the gate increases, V
T
of the transistor increases as a consequence of a reverse narrow channel effect (R-NCE).
As the R-SCE and the R-NCE both occur in case where the STI is used, it becomes more difficult in terms of designing the gate when a transistor having different V
T
is designed during the dual threshold voltage process. Thus, it is not easy to control the efficiency of the device.
When the line width is reduced down to below 0.5 micron, the problem of the R-NCE gets worse. In particular, the process below 0.35 micron produces serious effect to the device. It was known that the V
T
adjustment and the anti-punch through layer provided by performing global implantation gradually lose their effect due to the R-NCE. As a result, V
T
is unable to reach an expected value and the MOS transistor can not maintain its normal operation. However, such V
T
reduction may cause an increase in the subthreshold current. This leads to a poor reliability for the device while the product yield is reduced.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a MOS transistor, wherein the method combines a dual threshold voltage process and a local channel implantation for reducing the junction capacitance while improving the device efficiency.
According to the invention, the fabrication method for a MOS transistor is provided, with the STI serving as the device isolation, so that the R-NCE is prevented. Therefore, in the process below 0.25 micron, V
T
of the transistor is maintained within the working range so as to improve the reliability of the device.
As embodied and broadly described herein, the invention provides a fabrication method for a MOS transistor. The method involves forming a first gate oxide layer and a second gate oxide layer of different thicknesses on the substrate which is formed with the STI. A plurality of wells isolated with the STI are then formed in the substrate, wherein the wells include a first P-well and a first N-well corresponding to the first gate oxide layer, as well as a second P-well and a second N-well corresponding to the second gate oxide layer. A pattern mask is formed on the first gate oxide layer and the second gate oxide layer, wherein the pattern mask has an opening which exposes a channel from one of the wells. With the pattern mask serving as an ion implantation mask, a local channel implantation is performed to form two implantation regions in one of the wells below the opening for providing the V
T
adjustment and the anti-punch through layer, respectively. The pattern mask is then removed. The steps for forming the pattern mask, performing the local channel ion implantation, and removing the pattern mask are repeated in order to form two implantation regions in channels from rest of the well regions. Finally, a gate is formed on the substrate, while a source/drain (S/D) region is formed in the substrate.
The invention provides a method for fabricating a MOS transistor, which method forms a first gate oxide layer and a second gate oxide layer on a substrate formed with a STI. A first well and a second well are then formed in the substrate, wherein the first well and the second well correspond to the first gate oxide layer and the second gate oxide layer respectively. A first implantation region and a second implantation region are formed simultaneously as a whole in the first well and the second well so as to serve as threshold voltage adjustment and anti-punch through, and the first well and the second well are of the same conductive type. Next, a third well and a fourth well are formed in the substrate, wherein the third well and the fourth well correspond to the first gate oxide layer and the second gate oxide layer respectively. A third implantation region and a fourth implantation region are formed simultaneously as a whole in the third well and the fourth well so as to serve as threshold voltage adjustment and anti-punch through. The third well and the fourth well are of the same conductive type but the third well has a different conductive type from the first well and the second well. A local channel ion implantation is performed, so that a fifth implantation region and a sixth implantation region are formed in the channel region of the first well and the third well to provide the threshold voltage adjustment and anti-punch through layer. The R-NCE brought upon by using STI is also prevented in this case. Lastly, a gate is formed on the substrate, while a S/D region is formed in the substrate.
In the layout where the STI serves as a device isolation, ions possessed with certain energy and concentration are selectively doped by local channel implantation into corresponding regions below the gate. This can be effective in preventing the V
T
reduction as the gate width decreases. As a result, the problem of the R-NCE is solved with an increase in the product yield. In addition, the implantation region in this case does not extend to the bottom of the S/D region formed subsequently, thus the junction capacitance between the S/D region and the substrate is effectively reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Chao Alice
Chou Jih-Wen
Lin Tony
Bowers Charles
Smoot Stephen W.
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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