Method of fabricating a MOS transistor with elevated...

Details Method of fabricating a MOS transistor with elevated... Method of fabricating a MOS transistor with elevated...

2006-04-25

2006-04-25

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S184000, C438S230000, C438S301000, C438S305000, C438S306000, C438S363000

Reexamination Certificate

active

07033895

ABSTRACT:
In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

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