Method of fabricating a MOS transistor on a semiconductor wafer

Details Method of fabricating a MOS transistor on a semiconductor wafer Method of fabricating a MOS transistor on a semiconductor wafer

2000-01-28

2001-02-20

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S230000

Reexamination Certificate

active

06190982

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a MOS transistor on a semiconductor wafer.
2. Description of the Prior Art
As the density of integration of semiconductor devices increases, complementary metal-oxide-semiconductor (CMOS) transistors have gradually taken the place of N-type metal-oxide-semiconductors (NMOS) in recent years. The CMOS transistor is typically composed of one PMOS transistor and one NMOS transistor. A PMOS transistor comprises a gate, a P-type source and drain (S/D) and an N-type silicon substrate.
Boron is generally used as a dopant in the prior art method to form a heavily doped drain (HDD) and an S/D region. However, owing to the small atomic volume of boron, the phenomenon of out diffusion is usually observed after using boron in an ion implantation process. Boron out diffusion effects will seriously influence the electrical properties of the MOS transistor, especially when the design line width is less than 0.18 micrometers or even less than 0.15 micrometers. In addition, using a silicon dioxide layer as an etching stop layer when forming spacers in the prior art method also results in oxide-enhanced diffusion (OED) effects during the ion implantation process. Furthermore, the silicon dioxide layer will increase the rate of boron out diffusion and decrease the boron concentration in the HDD. Consequently, there is a need to improve the manufacturing process of forming the PMOS transistor so as to enhance the quality of the semiconductor products.
Please refer to
FIG. 1
to to
FIG. 4

FIG. 1
to
FIG. 4
are cross-sectional diagrams of the prior art method of fabricating a PMOS transistor
30
on a semiconductor wafer
10
. As shown in
FIG. 1
, the semiconductor wafer
10
comprises a silicon substrate
12
, and an N-well
11
on the surface of the silicon substrate
12
isolated by a shallow trench
14
. The semiconductor wafer
10
also comprises a gate
22
, which is located on the surface of the N-well
11
. The gate
22
comprises a dielectric layer
20
located on the N-well
11
and a doped polysilicon layer
21
located on the dielectric layer
20
. The dielectric layer
20
, composed of silicon dioxide (SiO
2
), serves as a gate oxide layer of the PMOS transistor
30
. The doped polysilicon layer
21
serves as a gate electrode of the PMOS transistor
30
.
As shown in
FIG. 2
, a uniform liner oxide layer
16
, composed of silicon dioxide (SiO
2
), is first formed on the surface of the semiconductor wafer
10
. A P
−
ion implantation process is then performed to form an HDD
23
on the surface of the silicon substrate
12
adjacent to the gate
22
. The dosage of boron in the P
−
ion implantation process is about 1×10
14
to 5×10
15
atoms/cm
2
, and the energy of the boron ions is about 10 to 15 KeV. Next, a silicon nitride layer
18
is uniformly formed on the surface of the liner oxide layer
16
.
Basically, the liner oxide layer
16
is used as an etching stop layer when forming silicon nitride spacers. It also serves as a buffer layer to release thermal stress produced by the silicon nitride spacers. However, boron has a tendency to diffuse into the liner oxide layer
16
. As a result, it is difficult to control the concentration of boron in the HDD
23
in the prior art method. Furthermore, during the P
−
ion implantation process, the liner oxide layer
16
causes a serious dosage loss problem and OED effects.
Next, as shown in
FIG. 3
, a conventional etching back process is used to vertically remove a portion of the silicon nitride layer
18
down to the surface of the liner oxide layer
16
. The remaining portion of the liner oxide layer
16
on each wall of the gate
22
becomes a spacer
19
. A heavier doping process, or a P
+
ion implantation process, is then used to form an S/D
24
of the PMOS transistor
30
on the silicon substrate
12
adjacent to the gate
22
. Boron, or boron fluoride ions (BF
2
+
), with an energy of about 10 KeV and a dosage of about 2×10
15
to
1
×
10
16
atoms/cm
2
are usually used in the P
+
ion implantation process. Thereafter, an annealing process at a temperature of 1000 to 1050° C. is performed to diffuse the boron ions into the S/D
24
to achieve a desirable profile and to repair the damage done to the silicon substrate
12
from the ion implantation process.
Next, as shown in
FIG. 4
, a dry etching process is performed to etch the liner oxide layer
16
that is not covered by the spacer
19
. Then, a self-aligned silicide (salicide) process is performed. A metal layer (not shown) is first formed on the surface of the semiconductor wafer
10
that covers the gate
22
. A thermal process is next used to form a silicide layer
26
on top of the gate
22
and on the surface of the S/D
24
. A wet etching process is next used to remove the metal layer thereby completing the PMOS transistor
30
.
The liner oxide layer
16
can prevent channeling effects during the P
−
ion implantation process and can also prevent damage to the silicon substrate. Unfortunately, the liner oxide layer
16
also causes a serious dosage loss during the P
−
ion implantation process, which makes it difficult to precisely control the concentration of boron in the HDD
23
. In order to overcome the problem of dosage loss, boron ions with higher energy must be used during the P
−
ion implantation process in the prior art method. However, these more energetic ions will result in undesirable deeper junction depths and OED effects, as well as short channel effects. In addition, out diffusion of boron into the liner oxide layer
16
also causes a decrease of the concentration of boron in the HDD
23
.
SUMMARY OF THE INVENTION
It is therefore a primary objective of this invention to fabricate a MOS transistor on a semiconductor wafer to solve the above-mentioned problems.
In a preferred embodiment, the present invention relates to a method of fabricating aMOS transistor on a semiconductor wafer. The semiconductor wafer comprises a silicon substrate. The method comprises:
forming a gate in a predetermined area on the surface of the semiconductor wafer;
performing a first ion implantation process to form a doped area on the surface of the silicon substrate adjacent to the gate, the doped area serving as a heavily doped drain (HDD);
forming a uniform and oxygen-free dielectric layer on the surface of the semiconductor wafer that covers the gate;
forming a spacer on each wall of the gate; and
performing a second ion implantation process to form a source and a drain on the surface of the silicon substrate adjacent to the spacer.
It is an advantage of the present invention that the method of fabricating a PMOS transistor on a semiconductor wafer can prevent dosage losses and deep junction depths because a liner oxide layer is not used in the HDD formation process. Furthermore, the oxygen-free dielectric layer can prevent both OED effects and the loss of boron from the HDD.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5736446 (1998-04-01), Wu
patent: 5858843 (1999-01-01), Doyle et al.
patent: 6074923 (2000-07-01), Lee
patent: 6083783 (2000-07-01), Lin et al.
patent: 6096591 (2000-08-01), Gardner et al.
patent: 6100148 (2000-08-01), Gardnet et al.

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