Method of fabricating a MOS transistor having SEG silicon

Details Method of fabricating a MOS transistor having SEG silicon Method of fabricating a MOS transistor having SEG silicon

2000-02-15

2001-11-13

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S194000, C438S226000, C438S231000, C438S230000

Reexamination Certificate

active

06316303

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89100307, filed Jan. 11, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a metal-oxide-semiconductor (MOS) transistor. More particularly, the present invention relates to a method of fabricating a MOS having selective epitaxial growth (SEG) silicon.
2. Description of Related Art
As the line width of MOS is reduced to or less than 0.1 &mgr;m according to the reduced design rule, in order to increase the margin for patterning a contact window, the SEG Si is gradually applied to the process of contact window where the source/drain region is exposed. However, there are still several problems with regard to the SEG Si that need to be overcome.
FIG. 1
is a schematic, cross-sectional view of a MOS having SEG Si. A gate
102
is formed on the substrate
100
. The gate
102
is isolated from the substrate
100
by a gate oxide layer
104
and has an insulating spacer
106
formed on its sidewall. A source/drain region
108
is formed in the substrate
100
, close to the gate
102
, and a lightly doped region
110
is formed in the substrate
100
between the gate
102
and the source/drain region
108
. After the formation of the above structure, SEG Si
112
a,
112
b
is then formed on the gate
102
and the source/drain region
108
.
Normally, the epitaxial silicon
112
a,
112
b
should grow with the same orientation as that of the substrate
102
when the chemical reactants and the system parameters are controlled well. The epitaxial silicon
112
a,
112
b,
however, becomes a polysilicon layer because of dopants in the source/drain region
108
. Polysilicon is silicon composed of many, randomly arranged crystal unit cells, usually leading to a rough surface. Therefore, when the silicide is subsequently formed on SEG Si
112
a,
112
b,
the silicide has an orientation similar to the polysilicon. As a result, the SEG Si
112
a,
112
b
having sharp grains induces current leakage between the silicide and the substrate
100
, which is known as the ‘dopant effect’. Accordingly, one of the troubles of SEG Si
112
a,
112
b
is that the quality of the SEG Si
112
a,
112
b
is varied with the dopants in the source/drain region
108
, as illustrated in FIG.
1
. Such phenomenon causes difficulty in the subsequent processes and leads to poor device quality, especially when the SEG Si is formed on a PMOS.
In addition, the SEG Si
112
a,
112
b
grows at a high temperature and is formed after the formation of the lightly doped region
110
. Such a high temperature, as is required to form the SEG
112
a,
112
b,
makes the lightly doped region
110
diffuse outwardly so that the channel length becomes shorter when the line width is reduced. As a result, the short channel effect or the hot carrier effect are induced and cause device failure.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a MOS transistor having SEG Si, thereby eliminating such problems as the dopant effect to improve the performance of the MOS transistor.
As embodied and broadly described herein, the invention provides a method of fabricating a MOS transistor having SEG Si. A gate is formed on a substrate and a spacer is formed on the sidewall of the gate. A SEG Si is formed over the substrate and a source/drain region is then formed in the substrate beside the spacer. The spacer is removed and an ultra shallow junction is formed in the substrate beside the gate.
The source/drain region is formed by a first ion implantation so that the ions penetrate through the SEG Si into the substrate. After removing the spacer, the surface of the substrate adjacent the gate is exposed and a second ion implantation is thus performed to form the ultra shallow junction in the exposed substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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