Method of fabricating a MOS transistor

Details Method of fabricating a MOS transistor Method of fabricating a MOS transistor

2000-04-26

2001-09-25

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S486000, C438S230000, C438S305000, C438S564000

Reexamination Certificate

active

06294415

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates a method of fabricating a MOS transistor on a semiconductor wafer, and more particularly, to an economic method of fabricating a MOS transistor on a semiconductor wafer.
2. Description of the Prior Art
Metal oxide semiconductor (MOS) transistors are in wide use in many electric devices. A MOS transistor has four terminals: the source, the drain, the gate and the substrate. The gate structure usually includes a polycrystalline silicon layer, or a polysilicon layer, and a silicide layer such as cobalt silicide (CoSi
2
). When a gate voltage greater than the threshold voltage of a MOS transistor is applied to the gate, a channel forms between the source and the drain due to strong inversion.
During the manufacturing process of a MOS transistor, the semiconductor wafer usually experiences several heating, or thermal, processes that are performed at high temperatures, such as 1000 to 1100° C. Unfortunately, this leads to an increasing thermal budget and, as the line width shrinks down to 0.18, 0.15 micrometers or lower, influences the precision when controlling the doping concentration of the heavily doped drain (HDD) region.
Please refer to
FIG. 1
to FIG.
4
.
FIG. 1
to
FIG. 4
are cross-sectional diagrams of fabricating a MOS transistor on a semiconductor wafer
10
according to the prior art. As shown in
FIG. 1
, a gate
20
is first formed on the semiconductor wafer
10
. The semiconductor wafer
10
comprises a plurality of shallow trenches
18
. The gate
20
comprises a gate oxide layer
22
formed on the surface of a silicon substrate
12
, and a doped polysilicon layer
24
formed on the gate oxide layer
22
. A liner oxide layer
26
composed of silicon oxide is deposited to cover the surface of the silicon substrate
12
and the gate
20
. A silicon nitride layer (not shown) is then formed on the liner oxide layer
26
and an etching back process is performed to etch the silicon nitride layer and the liner oxide layer
26
down to the surface of the silicon substrate
12
. The remaining silicon nitride layer adjacent to the gate
20
forms spacers
28
.
Subsequently, a first ion implantation process is performed using the gate
20
and the spacers
28
as hard masks to form a doped area (not shown). An annealing process is performed at a temperature of between 1000 to 1100° C. (1832 to 2012° F.) to form a source
14
and a drain
16
.
As shown in
FIG. 2
, the spacers
28
and the liner oxide layer
26
are removed and a second ion implantation using the gate
20
as hard masks is performed to dope the silicon substrate
12
adjacent to the gate
20
. An annealing process at a temperature of between 800 to 1000° C. (1472 to 1832° F.) is used to form a heavily doped drain (HDD) region
30
.
As shown in
FIG. 3
, A silicon oxide layer
34
composed of silicon dioxide is deposited on the semiconductor wafer
10
and a low pressure chemical vapor deposition (LPCVD) at a temperature of between 750 to 800° C. (1382 to 1472° F.) is performed to deposit a silicon nitride layer (not shown) on the semiconductor wafer
10
. A reactive ion etching process is used to form a spacer
36
adjacent to the gate
20
and portions of the silicon oxide layer
34
formed on the source
14
the drain
16
and the gate
20
are removed. A self-aligned silicide (salicide) process is performed to deposit a cobalt metal layer
38
on the surface of the silicon substrate
12
and the surface of the gate
20
. A rapid thermal process (RTP) is then performed at a temperature of between 700 to 850° C. (1292 to 1562° F.) to form the salicide
32
. The non-reacting portions of the cobalt metal layer
38
are removed.
The drawback in the prior art method is that the semiconductor wafer experiences several high-temperature thermal processes. For example, the annealing process is performed at a temperature of between 800 to 1000° C. (1472 to 1832° F.) to form the HDD region
30
, the LPCVD process is used at a temperature of between 750 to 850° C. (1382 to 1562° F.) to deposit a silicon nitride layer and the rapid thermal process is performed at a temperature of between 700 to 850° C. (1292 to 1562° F.) to form the salicide. These high-temperature processes may result in undesirable diffusion of the dopants in the HDD region
30
and the expansion of the area of the HDD region
30
, decreasing the channel length and thus inducing short channel effects. This becomes much worse when using B or BF
2
+
as a dopant because the atomic mass of the B or BF
2
+
is smaller than P.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide an economic method of fabricating a MOS transistor on a semiconductor wafer that prevents HDD dopant diffusion and reduces the thermal budget.
According to the present invention, a gate is formed on the surface of the silicon substrate. A first silicon oxide layer is formed on the surface of the semiconductor wafer to cover the surface of the silicon substrate and the surface of the gate. A first spacer is then formed on the surface of the first silicon oxide layer adjacent to the gate. A source and a drain are formed in the silicon substrate adjacent to the first spacer. The first spacer and the first silicon oxide layer are removed. A pre-amorphization implant (PAI) process is performed with germanium (Ge) as a dopant. A first ion implantation process is used to dope the silicon substrate adjacent to the gate. A second silicon oxide layer is formed to cover the gate. A PECVD process is performed to form a second spacer on the surface of the second silicon oxide layer adjacent to the gate. Finally, the second silicon oxide layer over the source, drain and gate is removed and a self-alignment silicide (salicide) process is performed to form a silicide layer on the surface of the source, drain and gate.
It is an advantage that the present invention uses the PAI process to dope the silicon substrate adjacent to the gate and then drives the dopants formed in the silicon substrate during the first ion implantation process into the silicon substrate to form the HDD region by virtue of the salicide process.


REFERENCES:
patent: 5908307 (1999-06-01), Talwar et al.
patent: 6096628 (2000-08-01), Greenlaw et al.
patent: 6136636 (2000-10-01), Wu
patent: 6146934 (2000-11-01), Gardner et al.

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