Method of fabricating a MOS device with a salicide structure

Details Method of fabricating a MOS device with a salicide structure Method of fabricating a MOS device with a salicide structure

1998-05-08

1999-09-14

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438 96, 438264, 438303, 438529, H01L 21336

Patent

active

059536160

ABSTRACT:
A method of fabricating an MOS device that includes self-aligned suicides, the method including two amorphization implantations, both of which follow formation of the self-aligned source/drain regions of the device but precede formation of the self-aligned suicides. The first consists of implantation of low-energy heavy ions, preferably of energies 15-20 keV, while the second consists of implantation of more energetic heavy ions, preferably of energies at least 40 keV.

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patent: 5858849 (1999-01-01), Chen
"A Ti Salicide Process for 0.10 .mu.m Gate Length CMOS Technology", Kittl et al., Symposium on VLSI Technology Digest of Technical Paper, pp. 14-15.

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