Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-07-07
2001-06-12
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000
Reexamination Certificate
active
06245626
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to fabrication of a semiconductor device. More particularly, the present invention relates to a method of fabricating a metal-oxide-semiconductor transistor (MOS transistor).
2. Description of Related Art
As the integration of the semiconductor device is increased, the size of the device is gradually decreased according to the reduced design rule. However, the resistance of the circuit becomes higher and higher when the material of the wiring line remains the same while the size is reduced.
Some methods to overcome the high sheet resistance of the poly gate and the source/drain junction have been developed in prior technique. One such method is a self-aligned silicide (salicide, SAC) process. SAC forms a metal silicide layer on the surface of the poly gate and the source/drain region, such that the sheet resistance of the poly gate and the source/drain region is lowered.
However, in the deep sub-micron level of semiconductor process, the surface area of the poly gate and the source/drain region provided to form a salicide becomes quite small, which results in a narrow line-width effect in the fabrication of salicide. In order to increase the area for salicide formation, the spacer beside the gate is over-etched to lower the height of the spacer so as to expose an upper edge of the poly gate sidewall, such that the area for forming the salicide is increased.
Although the high sheet resistance is improved by this method, other problems are created. The longer the spacer is over-etched, the shorter the spacer is, and the width of the spacer is reduced. The reduced width of the spacer causes relevant problems, such as a short channel effect due to the reduced width of the lightly doped drain (LDD). Therefore, it is difficult to control the time for which the spacer is over-etched. In addition, since the substrate surface of the source/drain region is exposed during over-etching, the substrate is easily damaged because of prolongation of etching time, which damage leads to current leakage.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a MOS transistor, thereby respectively controlling the width and the height of the spacer. The method not only provides enough space for the formation of salicide to reduce resistance of gate, but also control the width of the spacer, which prevents the reduction of spacer width varied by reduced height and avoids damage to the substrate.
As embodied and broadly described herein, the invention provides a method of fabricating a MOS transistor. A substrate has a gate formed thereon. An ion implantation is performed to form a LDD in the substrate beside the gate. A spacer is formed on the sidewall of the gate. A sacrificial layer is formed over the substrate to cover the gate and the spacer. A portion of the sacrificial layer is removed until the sacrificial layer level is lower than the gate, such that a portion of the spacer is exposed. Thereafter, using the sacrificial layer as a stop layer, the exposed spacer is removed to expose a portion of the sidewall of the gate. The sacrificial layer is then removed. A source/drain region is then formed in the substrate beside the spacer by a heavy ion implantation.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5015598 (1991-05-01), Verhaar
patent: 5221632 (1993-06-01), Kurimoto et al.
patent: 5672544 (1997-09-01), Pan
patent: 6046105 (2000-04-01), Kittl et al.
Chen Chun-Lung
Cheng Wen-Hua
Hsiao Hsi-Mao
Lin Hsi-Chin
Chaudhari Chandra
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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