Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-04-25
2001-08-07
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S637000
Reexamination Certificate
active
06271082
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for an integrated circuit (IC). More particularly, the present invention relates to a method of fabricating a mixed circuit capacitor.
2. Description of Related Art
A mixed circuit generally means a circuit having both a digital device and an analog device in a logic area of a semiconductor chip. The digital device can be an inverter, and an adder, whereas the analog device can be an amplifier, an analog/digital (A/D) converter, and so on. Typically, the mixed circuit has a capacitor structure therein for storing charges.
FIGS. 1A and 1B
are schematic, cross-sectional diagrams illustrating a conventional method for fabricating a mixed circuit capacitor.
Referring to
FIG. 1A
, in the conventional fabrication process for the mixed circuit, a fabrication process for the capacitor begins with coating a metal layer
102
for forming a lower electrode on a substrate
100
. Then, a dielectric layer
104
and a metal layer
106
for forming an upper electrode are formed in sequence on the metal layer
102
, so that the dielectric layer
104
is located between the upper electrode and the lower electrode. The metal layer
106
and the dielectric layer
104
are patterned, followed by patterning the metal layer
102
so as to result formation of the capacitor, as shown in FIG.
1
B.
The capacitor formed as described above has, in terms of area, a smaller upper electrode than the lower electrode, while the dielectric layer
104
is very thin. Therefore, an etching process can not stop on the dielectric layer
104
, when the metal layer
106
is patterned to form the upper electrode. As a result, the dielectric layer
104
is usually etched through by an etching solution, so that a part of the metal layer
102
below the metal layer
106
is exposed. This produces a problem, such as a sidewall leakage.
SUMMARY OF THE INVENTION
The invention provides a fabrication method for a capacitor applicable to a fabrication process for a mixed circuit. The method comprises of forming in sequence a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a conductive region. A first opening is formed in the second dielectric layer, said opening is located above the conductive region. A second opening is then formed in the stop layer and the first dielectric layer, wherein the first opening and the second opening form a dual damascene opening which exposes the conductive region. The dual damascene opening is then filled with a first conductive layer so as to form a via plug and a lower electrode of the capacitor for connecting to the conductive region. A third dielectric layer, which is located between the lower electrode and a subsequently formed upper electrode, is formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby the upper electrode for completely covering the lower electrode is formed.
As embodied and broadly described herein, the invention provides a fabrication method for a circuit. The method comprises of forming in sequence a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a first conductive region and a second conductive region. A first opening is formed in the second dielectric layer, said opening is located above the first conductive region. A second opening is then formed in the stop layer and the first dielectric layer, wherein the first opening and the second opening are combined to form a dual damascene opening which exposes the conductive region. A third opening is then formed in the second dielectric layer, the stop layer, and the first dielectric layer, wherein the third opening exposes the second conductive region. The dual damascene opening and the third opening are then filled with a first conductive layer so as to form a first via plug and a lower electrode of the capacitor for connecting to the first conductive region, and a second via plug for connecting to the second conductive region. A third dielectric layer, which is located between the lower electrode and a subsequently formed upper electrode, is formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby the upper electrode for completely covering the lower electrode and a third conductive layer for connecting the second via are formed.
According to the present invention, the metal damascene process is adopted to fabricate the lower electrode of the capacitor and the via plug. Therefore, this prevents problems, such as an overlap error and a process bias that occur in the conventional fabrication process for the capacitor. Accordingly, both the device reliability and the process margin are improved.
Also, since the capacitor is formed using the metal damascene process in the dielectric layer having a planar surface, an overall surface of the semiconductor device remains planarized.
According to the present invention, the lower electrode is completely covered by the upper electrode which has a projection area larger than that of the lower electrode. So, the surface of the lower electrode is not exposed during the etching step for forming the upper electrode. Therefore, this prevents the occurrence of the sidewall leakage in the capacitor, when the dielectric layer and the lower electrode are etched through in the conventional process for patterning the upper electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5631188 (1997-05-01), Chang et al.
patent: 5924011 (1999-07-01), Huang
patent: 6017817 (2000-01-01), Chung et al.
patent: 6171899 (2001-01-01), Liou et al.
Hou Chia-Hsin
Jung Tz-Guei
Ko Joe
Lin Jyh-Kuang
Chaudhari Chandra
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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