Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1996-03-29
1998-05-19
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438299, 438303, 438230, H01L 21336
Patent
active
057535566
ABSTRACT:
A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-thorough stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.
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Abe Katsunori
Fujino Seiji
Hattori Tadashi
Katada Mitsutaka
Muramoto Hidetoshi
Nguyen Tuan H.
Nippondenso Co. Ltd.
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