Method of fabricating a memory device having a long data...

Details Method of fabricating a memory device having a long data... Method of fabricating a memory device having a long data...

2000-11-21

2001-12-11

Fahmy, Jr., Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S256000, C438S397000

Reexamination Certificate

active

06329238

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device and a method of fabricating the same and, more particularly, to a semiconductor memory device that is microscopic in size and long in storage retention time and especially suitable for a dynamic random access memory (hereafter referred to as DRAM) and a method of fabricating such a semiconductor memory device.
2. Description of the Prior Art
The DRAM has been increasing in integration density at a rate as high as four times every three years. Currently, DRAMs of which integration densities are 16 megabits and 64 megabits are mass-produced and mass-production of gigabit-order DRAMs is being planned. Such high integration has been achieved miniaturizing the planar and depth dimensions of the DRAM. However, the miniaturization lowers the signal-to-noise ratio because of the reduction in the amount of charge that can be built up and makes conspicuous troubles such as signal reversal due to the incidence of alpha ray, presenting a serious problem of reliability maintenance.
Consequently, a memory cell that can increase storage capacity has been strongly desired. For such a memory cell, Japanese Published Unexamined Patent Application No. Sho 53-108392 (Japanese Published Examined Patent Application No. Sho 61-55528) discloses a structure as shown in FIG.
15
. The memory cell having the disclosed structure is called a stacked capacitor cell (STC) in which a part of a storage capacitor is stacked on a switch transistor or an isolation insulating transistor. This memory cell is expected to replace the conventional planar capacitor cell.
Referring to
FIG. 15
, reference numeral
2
.
1
denotes a semiconductor substrate, reference numeral
2
.
2
an isolation insulating film, reference numeral
2
.
3
a channel portion of a switching transistor, reference numerals
2
.
4
and
2
.
5
impurity diffused layers, reference numeral
2
.
6
a gate insulating film, reference numeral
2
.
7
a word line providing the gate electrode of switching transistor, reference numeral
2
.
9
a bit line, reference numerals
2
.
10
and
2
.
14
interlayer insulating films, reference numeral
2
.
11
a lower electrode of storage capacitor, reference numeral
2
.
12
a dielectric film of storage capacitor, reference numeral
2
.
13
a plate electrode (upper electrode) of storage capacitor, and reference numeral
2
.
15
a wiring metal. The bit line
2
.
9
is electrically connected to the impurity diffused layer
2
.
4
through an extended electrode
2
.
8
. The lower electrode
2
.
11
is electrically connected to the impurity diffused layer
2
.
5
.
With the conventional STC cell shown in
FIG. 15
, the lower electrode
2
.
11
of the storage capacitor can be extended over the word line
2
.
7
, so that far greater storage capacitance can be realized than that of the planar capacitor cell that uses only the surface of semiconductor substrate as a storage capacitor.
The STC cell shown in
FIG. 15
is fabricated through the following processes. First, a relatively thick (about 100 to 1000 nm) silicon oxide film for electrically separating elements is grown on the semiconductor substrate
2
.
1
made of single-crystal silicon by known thermal oxidation to form the isolation insulating film. The gate electrode of transistor
2
.
6
(about 5 to 50 nm) is grown by known thermal oxidation. Then, an impurity-doped polycrystalline silicon film is formed, which is worked into a predetermined shape by known photo-lithography and dry-etching to form the word line
2
.
7
. Using the word line
2
.
7
as a mask, an impurity having a different conductive type from that of the semiconductor substrate
2
.
1
is introduced into the same by a known ion implantation technique. Then, predetermine thermal processing is performed to activate the above-mentioned doped impurity to form the impurity-diffused layers
2
.
4
and
2
.
5
.
Next, a polycrystalline silicon film of the same conductive type is formed by known CVC (Chemical Vapor Deposition) such that the film comes in contact with the above-mentioned impurity-diffused layer
2
.
5
. The unwanted portions of the film thus formed are removed by etching to form the lower electrode
2
.
11
of the storage capacitor. As is clear from
FIG. 15
, the above-mentioned lower electrode
2
.
11
is formed also extending over the word line
2
.
7
and the isolation insulating film
2
.
2
, so that the area of the lower electrode
2
.
11
of the storage capacitor becomes extremely large, resulting in an increased amount of charge to be stored.
SUMMARY OF THE INVENTION
However, the above-mentioned conventional STC cell involves the following problems that remain to be solved.
For the requirement to enhance both of device operation speed and packing density of memory cells, miniaturization of planar dimensions is performed, resulting in about 0.1 to 0.2 microns of the width of the word line
2
.
7
in a memory device of 10-megabit order.
However, if the planar dimensions are miniaturized in the above-mentioned structure in order to realize the high device operation speed, a so-called punch-through phenomenon is caused, making it difficult to obtain good device characteristics. To overcome this problem, it is conventionally generally practiced to make the junction depth as shallow as possible. The typical junction depth is about 0.1 micron. In order to realize such a shallow junction depth, the thermal processing for impurity activation to be performed after the ion implantation into the semiconductor substrate
2
.
1
is performed at a relatively low temperature and a relatively short time.
However, the execution of such a low-temperature and short-time thermal processing causes a new problem of causing an electrical defect or a so-called deep trap in the impurity implantation into the semiconductor substrate
2
.
1
. This problem increases the leakage current at the pn junction between the semiconductors of different conductive types, making it difficult to hold a predetermined storage retention time. Consequently, if the area of the storage capacitor is increased by the STC cell, the increase in the leakage current from the impurity diffused layer
2
.
5
electrically connected to the lower electrode
2
.
11
prompts the discharge of the storage charge, thereby making it difficult to form a shallow junction to pose limitations on the miniaturization of device structures.
It is therefore an object of the present invention to provide a miniaturized semiconductor memory device that is extremely small in leakage current and sufficiently long in storage retention time and a method of fabricating such a semiconductor memory device with ease.
In carrying out the invention and according to one aspect thereof, there is provided a semiconductor memory device comprising: a plurality of active regions formed on a semiconductor substrate; a metal oxide semiconductor transistor formed on the plurality of active regions; a separation insulating film formed between adjacent ones of the plurality of active regions for electrically separating the same from each other; a lower electrode of a storage capacitor, the lower electrode being electrically connected to one of a pair of diffused layers of the metal oxide semiconductor transistor formed in a surface region of the plurality of active regions and having a conductor type reverse to that of the semiconductor substrate, the lower electrode extending over the active region and the separation insulating film; a dielectric film and an upper electrode of the storage capacitor, the dielectric film and the upper electrode being stacked on the lower electrode; and a conductive film arranged in a rim portion in the separation insulating film in a manner opposed to the semiconductor substrate with an insulating film in between; wherein the lower end portion of the lower electrode is electrically connected to the upper end portion of the conductive film.
The above-mentioned deep traps for increasing the lead current are induced by th

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