Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-14
2001-02-27
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06194274
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a mask ROM by which the bury implantation step can be shifted and combined with the back-end process, thereby improving the efficiency of the delivery of mask ROMs.
2. Description of the Related Art
FIGS. 1A
to
1
C shows the conventional process of fabricating a mask ROM in cross-sectional view. First, a plurality of MOS transistors serving as memory cells are formed in a semiconductor substrate
1
, as depicted in FIG.
1
A. In
FIG. 1A
, numeral
2
indicates an isolation structure which is usually a field oxide layer formed via LOCOS method; numeral
3
indicates the polysilicon gate of one of the MOS transistors (the gate oxide layer is not shown) and numeral
4
indicates the source and drain (n
+
diffusion regions) of one of the MOS transistors. Next, a photoresist layer
5
is formed over the MOS transistors, and is then defined and patterned using a code mask in conjunction with photolithography, as depicted in FIG.
1
B. Then, a bury implantation is carried out to complete the coding process of the mask ROM, as depicted in FIG.
1
C.
In the bury implantation step, MOS transistors with their gates revealed by the photoresist layer
5
will be defined as the memory cells having coded data “0”. On the other hand, MOS transistors with their gates covered by the photoresist layer
5
will be defined as the memory cells having coded data “1”.
After the bury implantation step, subsequent back-end process steps are carried out such as: (a) removing the photoresist layer
5
; (b) forming a BPSG layer over the MOS transistors; (c) carrying out a first metalization process; (d) forming a dielectric layer; (e) forming via holes by using a via mask; (f) carrying out a second metallization process etc., and finally forming a passivation layer.
IC manufacturers typically fabricate in advance a mask ROM prepared structure as described in FIG.
1
A. When given orders for mask ROMs by customers, IC manufacturers start to fabricate the code mask according to a code specification required by the customers. Then, the code mask is used to pattern the photoresist layer to reveal the MOS transistors to be implanted (coded), as described in FIG.
1
B. Next, the bury implantation process is carried out for encoding memory data, thereby completing the mask ROM required by the customers as described in FIG.
1
C. However, the mask ROM can not deliver to the customers, until the steps (a)-(f) of the back-end process are performed. Consequently, the delivery of finished products (mask ROM) to the customers depends on the required time for completing the above process.
For IC manufacturers, prompt delivery of finished products means profits and competitive edge. If the bury implantation step can be shifted and combined with the back-end process, then the fabrication of mask ROMs can be simplified and the efficiency of delivery is improved.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a method of fabricating a mask ROM by which the bury implantation step can be shifted and combined with the back-end process thereby improving the efficiency of delivery of mask ROMs.
The present invention achieves the above-indicated objects by providing a method of fabricating a mask ROM that comprises the following steps.
First, a semiconductor substrate is provided with a plurality of memory cells formed therein; wherein each of the memory cells is a MOS transistor.
Secondly, a first isolation layer is formed over the memory cells; wherein the first isolation layer is a BPSG layer.
Then, a combination layer is formed over the first isolation layer; wherein the combination layer comprises a plurality of middle conduction layers and a plurality of middle isolation layers (or at least a middle isolation layer) overlapping mutually. For example, the combination layer is formed by the following steps: forming a first metal layer (metal-
1
); forming an isolation layer (iso-
1
) over the first metal layer (metal-
1
), wherein the isolation layer (iso-
1
) is patterned and etched to form connect holes therein and reveal the first metal layer (metal-
1
); and then forming a second metal layer (metal-
2
) over the isolation layer (iso-
1
) electrically contacting to the first metal layer (metal-
1
) via the connect holes. In this way, the combination layer is formed by the metal layers (metal-
1
, metal-
2
) and the isolation layer (iso-
1
) overlapping mutually.
Subsequently, a second isolation layer, for example a dielectric layer, is formed over the combination layer and the first conduction layer.
A photoresist layer is formed and patterned over the second isolation layer by using a combination mask in conjunction with photolithography process; wherein a first and second pattern defined in the combination mask are transferred onto the patterned photoresist layer.
Etching process is carried out using the patterned photoresist layer as an etching mask layer, whereby contact holes defined by the first pattern are formed in the second isolation layer and the middle isolation layers to reveal some of the middle conduction layers (metal-
1
or metal-
2
), and encoding holes defined by the second pattern are formed in the second isolation layer, the middle isolation layers and the first isolation layer to reveal the gates of a portion of the MOS transistors (memory cells). Finally, a bury (or code) implantation process is performed to dope the gates of the MOS transistors in the encoding holes, therefore completing the encoding operation of a mask ROM.
Further, a metalization process is carried out to form a top metal layer electrically contacting to the middle conduction layers (such as metal-
1
and metal-
2
) via the contact holes and filling each of the encoding holes.
In the conventional method of fabricating mask ROMs, a code mask is used to define the encoding holes (FIG.
1
B), and a via mask is used during the back-end process to define the connect holes (or via holes) between the metal layers formed in metalization steps. According to the present invention, the via mask and the code mask are combined into the combination mask. Consequently, when the connect holes are formed to reveal the metal layers (metal-
1
or metal-
2
) out of the middle isolation layer, the encoding holes are also formed to reveal some specific memory cells out of the first isolation layer (BPSG) and the middle isolation layers such that the memory cells can coded by the bury implantation process. In this way, the implantation process is shifted and combined with the back-end process, thereby speeding the delivery of finished products.
REFERENCES:
patent: 5946576 (1999-08-01), Wen
patent: 0053654A2 (1982-06-01), None
Fourson George
Garcia Joannie A.
Winbond Electronics Corp.
LandOfFree
Method of fabricating a mask ROM does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a mask ROM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a mask ROM will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2567485