Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-26
2002-10-22
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S294000, C438S299000, C438S197000, C438S135000
Reexamination Certificate
active
06468870
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a method to fabricate of a lateral diffused Metal oxide semiconductor (LDMOS) transistor.
2) Description of the Prior Art
In many applications it is desirable to have a variety of logic devices, memory devices and device capable of withstanding large transients (hereon referred to as power devices) all on a single substrate. On type of power device is a diffused metal-oxide- semiconductor transistor (Tx) (DMOS).
Heretofore most lateral diffused Metal oxide semiconductor, (LDMOS) structures built on a substrate with one or more other device structures were formed by first forming a high voltage tank. The devices are isolated by field oxide (FOX) processes or shallow trench isolation (STI) regions. However, in a critical understanding, the inventors have found that the isolation (e.g., FOX) regions under the gate electrode have problems that lower the breakdown voltage.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,242,841 (Smayling et al.) and U.S. Pat. No. 5,491,105 (Smayling et al.) show LDMOS Tx processes.
U.S. Pat. No. 5,639,676 (Hshieh et al.) shows a trenched DMOS Tx process. U.S. Pat. No. 5,474,943 (Hshieh et al.) teaches a short trenched channel DMOS TX process.
However, an improved LDMOS process is needed that improves the breakdown voltages and reduces the problems with low breakdowns associated with the field oxide (FOX) regions.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a semiconductor device.
It is an object of the-present invention to provide a method for fabricating a lateral diffused Metal oxide semiconductor (LDHOS) Transistor.
It is an object of the present invention to provide a method to improve the breakdown voltage of the LDMOS.
To accomplish the above objectives, the present invention provides a method of manufacturing a LRMOS transistor having an e-field enhancement block under the gate electrode.
The invention begins by providing a high voltage well and a low voltage well in the substrate. Next, a first field oxide region is formed overlapping the low voltage and high voltage wells. The first field oxide region has bird beaks. Next, an important (e-field tolerance enhancement) dielectric block is formed over the bird beaks of the first field oxide region. After this the LDMOS device is completed by forming a gate stack over the dielectric block.
The invention's e-field enhancement dielectric block layer covers the bird's beaks of the field oxide regions. This e-field enhancement oxide layer relieves the e-field near the bird's beak, thus increasing the Breakdown voltage (BV) of the LDMOS transistor. According to simulations, the BV is improved by as much as 30%. The drain current the invention's device is larger than the conventional device, which enhances the current driving capability of the circuit.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5242841 (1993-09-01), Smayling et al.
patent: 5382536 (1995-01-01), Malhi et al.
patent: 5474943 (1995-12-01), Hshieh et al.
patent: 5491105 (1996-02-01), Smayling et al.
patent: 5512495 (1996-04-01), Mei et al.
patent: 5639676 (1997-06-01), Hshieh et al.
patent: 5903032 (1999-05-01), Duvvury
patent: 6251744 (2001-06-01), Su et al.
Chen Shih-Hui
Gong Jeng
Huang Kuo-Shu
Huang Tsung-Yi
Kao Chi-Hung
Ackerman Stephen B.
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
Trinh Michael
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