Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-09-02
2003-01-14
Lee, John R. (Department: 2881)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S290000, C438S291000, C438S305000, C438S306000, C257S262000, C257S288000
Reexamination Certificate
active
06506648
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to high power RF field effect transistors, and more particularly the invention relates to a method of fabrication and resulting structure with reduced hot electron injection and improved device operating characteristics.
Hot carrier injection (HCI) is a phenomena which reduces the reliability and affects the performance over time of metal insulator semiconductor field effect transistors (MISFET) and in particular the lateral diffused MOSFET (LDMOS) devices. HCI is a result of high peak electric field and impact ionization in the drain of MOSFET devices. For high power RF applications, power supply voltage, Vdd is typically well in excess of 25 volts. Higher voltage means higher electric field. For RF applications at frequencies above 1 GHz, short channel (gate length <1&mgr;) MOSFETs are used to minimize capacitances. The high Vdd results at high electric field and significant impact ionization or hot electrons. The hot electrons are injected into the gate oxide impacts the threshold voltage, Vth, and the transconductance, G
m
, compression behavior.
Typically, the drain doping is maximized in order to minimize the on-resistance, Rdson, of a MOSFET. Higher doping results in higher electric fields and higher carrier generation rates, which results in hot carrier injection into the gate dielectric. The hot electrons injected into the gate oxide near the drain of the MOSFET tends to shift some of the key transistor parameters over time. For example, a typical RF power LDMOS device has a positive shift in V
gs
arising from HCI. This translates into a negative drain current shift of minus 3.5%/decade-time (nominal value of drain current of 200 mA), and also results in a reduction in the maximum drain current for linear operation of approximately 20% over 15 hours of operation. This is illustrated in the curve of
FIG. 1
in which transconductance is plotted versus drain current before and after stress.
Davies et al. U.S. Pat. No. 5,155,563 discloses an LDMOS structure with an extended drain which is formed after gate patterning and which is designed to reduce HCI. The N-extended drain is self-aligned to the gate edge in order to minimize the gate to drain capacitance. As the N-extended drain dopant level is increased to reduce drain resistance, surface doping increases which increases peak electric field and impact ionization generation. Further, channel length is not minimized since N dopant diffusion under the gate is not impeded since the N-drain is not present during the channel drive.
Another device to reduce HCI is the low doped drain (LDD) MOSFET transistor which introduces a low doped drain (N−) under the gate and next to the drain contact. However, these devices can only be operated at low voltages since there is insufficient drain drift region to sustain high voltages.
Thus increasing the N-drain region doping results in excessive HCI, which reduces the reliability and stability of the devices over time. However, N-drain doping should be increased in order to improve linearity at high power levels (peak current) and reduce on-resistance of the device. However, N-drain doping cannot be maximized with prior art structures due to hot carrier injection problems.
SUMMARY OF THE INVENTION
In accordance with the invention, a fabrication process for a LDMOS device is provided in which an N-well for the drain drift region is formed prior to gate fabrication. This optimizes the doping profile of the N-drain region and the channel region of the resulting structure. RF performance of the device can be improved while reducing HCI related shifts in threshold voltage (Vth) over time and minimizing reduction in maximum device current over time.
The N-well can be formed at the beginning of the process using an optional mask. However, there is no need for complex processing such as the need for spacers in forming LDD devices. The N-well can be blanket doped or masked doped. The resulting structure can have a 50% reduction in impact ionization generation resulting in reduced HCI. Linearity of the device can be maximized without reducing reliability. Further, channel length is reduced.
REFERENCES:
patent: 5155563 (1992-10-01), Davies et al.
patent: 5286995 (1994-02-01), Malhi
patent: 5306652 (1994-04-01), Kwon et al.
patent: 5578860 (1996-11-01), Costa et al.
patent: 5696010 (1997-12-01), Malhi
patent: 5869875 (1999-02-01), Hebert et al.
patent: 5912490 (1999-06-01), Hebert et al.
patent: 5918137 (1999-06-01), Ng et al.
Hebert Francois
Ng Szehim Daniel
Cree Microwave, Inc.
Lee John R.
Souw Bernard
Woodward Henry K.
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