Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-06-07
2005-06-07
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S151000, C438S197000, C438S300000, C438S527000, C438S595000, C438S607000, C438S704000, C438S757000, C438S761000
Reexamination Certificate
active
06902980
ABSTRACT:
A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After formation of an LDD region a composite insulator spacer, comprised of an underlying silicon oxide spacer component and an overlying silicon nitride spacer component, is formed on the sides of a gate structure. Formation of a heavily doped source/drain is followed by removal of the silicon nitride spacer resulting in recessing of, and damage formation to, the heavily doped source/drain region, as well as recessing of the gate structure. Removal of a horizontal component of the silicon oxide spacer component results in additional recessing of the heavily doped source/drain region, and of the gate structure. A selective epitaxial growth procedure is then used to form a raised, single crystalline silicon structure on the recessed and damaged heavily doped source/drain and LDD regions, while a polycrystalline silicon structure is grown on the underlying recessed gate structure. Metal silicide is then formed on the raised, single crystalline silicon structure and on the polycrystalline silicon structure.
REFERENCES:
patent: 5296727 (1994-03-01), Kawai et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5581114 (1996-12-01), Bashir et al.
patent: 5949105 (1999-09-01), Moslehi
patent: 5994747 (1999-11-01), Wu
patent: 6165857 (2000-12-01), Yeh et al.
patent: 6197645 (2001-03-01), Michael et al.
patent: 6214673 (2001-04-01), Grebs et al.
patent: 6281085 (2001-08-01), Yeo
patent: 6287926 (2001-09-01), Hu et al.
patent: 6489206 (2002-12-01), Chen et al.
patent: 6562686 (2003-05-01), Lee
patent: 6777298 (2004-08-01), Roy et al.
patent: 6787425 (2004-09-01), Rotondaro et al.
patent: 6815770 (2004-11-01), Chien et al.
IBM Technical Disclosure Bulletin, Dec. 1988, vol. 31, issue 7, pp. 129-131.
K. De Meyer et al., “Raised Source/Drains with Disposable Spacers for Sub 100 nm CMOS technologies”, Extended Abstracts of Int'l Workshop on Junction Technology 2001, pp. 5-3-1 to 5-3-4.
Chang Chih-Sheng
Wang Yin-Pin
Elms Richard
Luhrs Michael K.
Taiwan Semiconductor Manufacturing Co. Ltd.
Thomas Kayden Horstemeyer & Risley
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