Method of fabricating a high density EEPROM cell

Details Method of fabricating a high density EEPROM cell Method of fabricating a high density EEPROM cell

1997-05-05

1999-01-05

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438263, H01L 218247

Patent

active

058562222

ABSTRACT:
A method of fabricating an EEPROM cell structure in a semiconductor substrate includes forming a layer of silicon oxide having a first thickness on the silicon substrate. N-type dopant is then introduced into the semiconductor substrate to define a buried region beneath the silicon oxide layer. Next, a tunnel window opening is formed in the silicon oxide layer to expose a surface area of the buried region. A layer of tunnel oxide is then grown in the tunnel window opening on the exposed surface of the buried region, such that the tunnel oxide has a thickness that is less than the thickness of the silicon oxide. A first layer of polysilicon is then formed on the structure resulting from the foregoing steps, followed by an overlaying layer of oxide.backslash.nitride.backslash.oxide (ONO) and an overlying layer of second polysilicon. The poly-2, ONO.backslash.poly-1 sandwich is then anisotropically etched to form first and second stacks which provide the floating gate/control gate electrodes for the EEPROM cell access transistor and the EEPROM cell storage cell structure, respectively.

REFERENCES:
patent: 5057446 (1991-10-01), Gill et al.
patent: 5379253 (1995-01-01), Bergemont
patent: 5587332 (1996-12-01), Chang et al.
patent: 5712178 (1998-01-01), Cho et al.
E.K. Shelton, "Low-Power EE-PROM Can Be Reprogrammed Fast", Electronics, pp. 89-92, Jul. 31, 1980.

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