Method of fabricating a gate structure of a field effect...

Details Method of fabricating a gate structure of a field effect... Method of fabricating a gate structure of a field effect...

2002-09-16

2004-07-06

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S719000, C438S723000, C438S743000, C438S712000, C438S714000, C438S715000, C438S717000

Reexamination Certificate

active

06759286

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for fabricating devices on semiconductor substrates. More specifically, the present invention relates to a method for fabricating a gate structure of a field effect transistor.
2. Description of the Related Art
Ultra-large-scale integrated (ULSI) circuits typically include more than one million transistors that are formed on a semiconductor substrate and cooperate to perform various functions within an electronic device. The transistors generally are complementary metal-oxide-semiconductor (CMOS) field effect transistors comprising a gate structure disposed between a source region and a drain region that are formed in the semiconductor substrate. The gate structure comprises a gate electrode and a gate dielectric. The gate electrode is provided over the gate dielectric and controls a flow of charge carriers in a channel region formed between the drain and the source regions to turn the transistor on or off. There is a constant trend to reduce a width of the channel region, as well as the width of the gate structure to thereby increase the overall speed of the transistor.
The topographic dimensions of a feature (i.e., transistor component or element such as a width of the gate structure) decrease as the number of transistors in the ULSI circuit increases. In a conventional fabrication process, a lithographically patterned photoresist mask is used during etch and deposition processes to form transistor components (e.g., an element of a field effect transistor such as a gate structure and the like). Consequently, a thickness of the photoresist mask also decreases as the feature becomes smaller. As such, the lithographic techniques become unable to precisely and accurately define the feature. For example, a thickness of the photoresist mask is limited to about 3000 Angstroms during fabrication of a feature having the topographic dimensions of about 0.13 &mgr;m. The designs utilizing features with the dimensions smaller than 0.13 &mgr;m require even thinner photoresist mask to transfer a pattern of the feature onto a layer on the substrate. Such photoresist masks are so thin that they cannot provide precise dimensional control of the features being formed or adequate protection to the underlying layers during plasma etch processes, e.g., processes used to form the gate structure of a field effect transistor.
Therefore, here is a need in the art for a method of fabricating narrow gate structure.
SUMMARY OF THE INVENTION
The present invention is a method of fabricating a gate structure of a field effect transistor (FET). The method comprises forming a hard mask upon the gate electrode layer, plasma etching a gate electrode, and contemporaneously forming a gate dielectric, as well as removing the hard mask using a plasma etch process. In one embodiment, the hard mask is formed to thickness of about 100 to 300 Angstroms and comprises at least one metal such as Al, Ti, W, Ta, and the like, or at least one dielectric such as HfO
2
, HfSiO
2
, Al
2
O
3
, and the like.


REFERENCES:
patent: 6037265 (2000-03-01), Mui et al.
patent: 6221784 (2001-04-01), Schmidt et al.
patent: 6461974 (2002-10-01), Ni et al.
patent: 6579809 (2003-06-01), Yang et al.

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