Method of fabricating a flash memory cell

Details Method of fabricating a flash memory cell Method of fabricating a flash memory cell

2000-08-11

2001-12-04

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S316000

Reexamination Certificate

active

06326263

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a flash memory cell, and more particularly, to a method of fabricating a flash memory cell having a self-aligned floating gate structure and an enhanced coupling ratio characteristic.
2. Description of the Prior Art
EEPROM (electrically erasable programmable read only memory) is a very popular memory device used in the electronics industry because it can store data in a non-volatile manner for more than 10 years, and it can be reprogrammed or erased many times. But one of the drawbacks of EEPROM devices is that their memory access time is quite slow compared to other memory devices. In order to solve this problem, a flash EEPROM device, or flash memory, was developed by Intel. In contrast to traditional EEPROM, the flash memory can erase recorded data a block at a time instead of a byte at a time, and this dramatically increases the memory access time.
The flash memory technology achieves high density due to a smaller memory cell size realized in a stacked-gate memory cell profile. A stacked-gate flash memory cell comprises a floating gate for storing electric charge, a control gate for controlling the charging of the floating gate, and a dielectric layer positioned between the floating gate and the control gate. Like a capacitor, the flash memory stores electric charge in the floating gate to represent a digital data bit of “1 ”, and removes charge from the floating gate to represent a digital data bit of “0”.
Please refer to
FIG. 1
to FIG.
7
.
FIG. 1
to
FIG. 7
are cross-sectional diagrams illustrating the processes of fabricating a flash memory cell on a semiconductor wafer
10
according to the prior art method. As shown in
FIG. 1
, the semiconductor wafer
10
comprises a silicon substrate
12
, a tunneling oxide layer
14
with a thickness of about 50 to 200 angstroms formed on the surface of the silicon substrate
12
, and a defined polysilicon layer
16
with a thickness of 500 to 1000 angstroms on the tunneling oxide layer
14
. The defined polysilicon layer
16
is formed within predetermined regions over the semiconductor wafer
10
using conventional lithographic and etching processes. These predetermined regions are known as active regions, and the defined polysilicon layer
16
, which functions as a gate electrode, defines the channel of a field-effect-transistor (FET). First, a sacrificial layer
18
, made of silicon nitride, is deposited on the surface of the semiconductor wafer
10
, covering the defined polysilicon layer
16
and the tunneling layer
14
. A developed and patterned photoresist layer
20
is then used to define the active regions
21
over the polysilicon layer
16
atop the sacrificial layer
18
. The memory cell of an EEPROM is formed within each of the active regions
21
.
As shown in
FIG. 2
, an anisotropic etching process is performed to etch the sacrificial layer
18
outside the active regions
21
, which is not covered and protected by the patterned photoresist layer
20
. Subsequently, a plasma ashing process and a series of cleaning processes are used to remove from the surface of the semiconductor wafer
10
the photoresist layer
20
, residues and byproducts formed during the previous etching processes. As shown in
FIG. 3
, after defining the active regions
21
in the sacrificial layer
18
, the semiconductor wafer
10
is subject to another dry etching process in which the defined sacrificial layer
18
acts as a hard mask. The silicon substrate
12
that is not covered by the sacrificial layer
18
is vertically etched in this etching process, thereby forming a shallow trench pattern
22
on the surface of the silicon substrate
12
.
Next, as shown in
FIG. 4
, a high-density plasma chemical vapor
20
deposition (HDPCVD) process is performed to deposit an HDP oxide layer
24
that fills the trench pattern
22
on the surface of the semiconductor wafer
10
. As shown in
FIG. 5
, using a chemical mechanical polishing (CMP) process, the HDP oxide layer
24
over the sacrificial layer
18
is removed, thus obtaining a planar topography that is beneficial to the following processes.
As shown in
FIG. 6
, using a wet etching process, such as hot phosphoric acid etching, the sacrificial layer
18
is completely removed and the top face of the polysilicon layer
16
is therefore exposed. A polysilicon layer
26
is then formed on the semiconductor wafer
10
using a conventional chemical vapor deposition method. Thereafter, a conventional lithographic process is performed to define the location of the floating gate over the polysilicon layer
26
and the polysilicon layer
16
by using a patterned photoresist layer
28
.
In
FIG. 7
, using the patterned photoresist layer
28
as a etch mask, an etching process is performed to remove the polysilicon layer
26
that is not covered by the photoresist layer
28
down to the surface of the HDP oxide layer
24
, thereby forming the floating gate
27
. The floating gate consists of the polysilicon layer
26
and polysilicon layer
16
. After removing the photoresist layer
28
, a thin oxidized-silicon nitride-silicon oxide (ONO) dielectric layer
32
is formed on the exposed surface of the floating gate
27
. Finally, a control gate of doped polysilicon
34
is formed over the ONO dielectric layer
32
.
There are two weaknesses of the prior art method of fabricating a flash memory, which are as follows: (1) occurrences of misalignment when defining the floating gate
27
using the photoresist layer
28
increases as the line width shrinks, and (2) the coupling ratio of the flash memory cell according to the prior art method is insufficient for future requirements. Coupling ratio is an index that is usually used to evaluate the performance of a flash memory cell. The higher the coupling ratio, the better the performance of the flash memory cell. An inferior coupling ratio characteristic of the flash memory leads to undesirable higher reading currents, and higher programming and erasing voltages. Furthermore, the misalignment phenomenon reduces the yield of flash memory products.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of fabricating a flash memory cell having a self-aligned floating gate structure and a superior coupling ratio characteristic, and to provide a manufacturing process that can effectively enhance the performance of flash memory products.
In accordance with the objectives of the present invention, a new method of fabricating a high coupling ratio flash memory cell is disclosed. A semiconductor wafer is first provided having a substrate. A tunneling oxide layer is formed on the substrate. A sacrificial layer defining an active region is formed over the tunneling oxide layer, and a defined first polysilicon layer is formed on the tunneling oxide layer within the active region, covered by the sacrificial layer. Briefly, the process sequence includes: performing an etching process using the sacrificial layer as a mask to form a shallow trench isolation (STI) pattern on the substrate, forming a dielectric layer on the semiconductor wafer that fills the STI pattern, performing a planarization process to remove the dielectric layer over the sacrificial layer, performing a first etch back process to remove a pre-selected thickness of the dielectric layer over the STI pattern, forming a second polysilicon layer on the semiconductor wafer, performing a second etch back process to form a spacer connecting with the first polysilicon layer, removing the sacrificial layer, forming an insulating layer on the surface of the spacer and the first polysilicon layer, forming a control gate on the insulating layer, and performing an ion implantation process to form a source and a drain on the substrate within the active region.
According to the present invention, two polysilicon spacers connecting with the first polysilicon layer, acting as portions of the floating gate, are formed. The two spacers and the first polysi

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