Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-05-17
2005-05-17
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S295000, C438S300000
Reexamination Certificate
active
06893918
ABSTRACT:
A method of fabricating a flash memory is provided. A substrate having several device isolation structures for defining an active region is provided. A tunneling dielectric layer and a patterned mask layer are sequentially formed over the active region of the substrate. A sacrificial layer is formed on the substrates. Thereafter, the sacrificial layer is patterned to retain a part of sacrificial layer on the device isolation structures. The patterned mask layer is removed, and a conductive layer that exposed the top section of the sacrificial layers is formed over the substrate. After removing the sacrificial layer, an inter-gate dielectric layer is formed over the substrate. A control gate is formed over the inter-gate dielectric layer. Finally, a source region and a drain region are formed in the substrate on each side of the control gate.
REFERENCES:
patent: 6656793 (2003-12-01), Jeong et al.
patent: 20040087086 (2004-05-01), Lee
Du Chien-Chih
Pittikoun Saysamone
Wang Leo
Dang Phuc T.
Jianq Chyun IP Office
Powerchip Semiconductor Corp.
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