Method of fabricating a flash memory

Details Method of fabricating a flash memory Method of fabricating a flash memory

2000-10-02

2001-12-18

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S259000, C438S266000, C438S267000

Reexamination Certificate

active

06331464

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89118399, filed Sep. 8, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method of fabricating a flash memory.
2. Description of the Related Art
Conventional non-volatile flash memory devices such as erasable programmable read only memories (EPROM), electronically erasable programmable read only memories (EEPROM), and flash memories do not lose their stored information when power is lost. Because these devices have superior information storage capacity, they are the subjects of ongoing related research.
Electronically erasable programmable read only memory (EEPROM) is a kind of non-volatile memory. Most EEPROM cells have two gates, including a floating gate made of polysilicon to store charge and a control gate used to control information storage. The floating gate is usually in a “floating” state. That is to say, no lines are connected to it. The control gate is often connected to a word line. A tunnel oxide layer and a dielectric layer are arranged between the substrate and floating gate and the floating gate and control gate, respectively. Additionally, source and drain regions are arranged in the substrate on both sides of the control gate.
Generally, as the gate-coupling ratio between the floating gate and the control gate increases, the work voltage necessary to operate the memory transistor decreases. As a consequence, the operational speed and efficiency of the flash memory increase tremendously. Methods for increasing the gate-coupling ratio (GCR) include: increasing the overlapped area between the floating and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the dielectric constant (k) of the dielectric layer between the floating gate and the control gate. Generally, to achieve an increase in the overlapped area between the floating and control gates and thus increase the gate-coupling ratio (GCR), the size of the floating gate has to be increased. However, this is not desirable for the demands of today's highly-integrated technologies.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method of fabricating a flash memory. The method comprises the steps of providing a substrate having a tunnel oxide layer, a first conductive layer and a first material layer formed thereon. A conductive spacer is formed on the sidewalls of the first conductive layer and the first material layer. A second material layer is formed on the substrate. A portion of the second material layer is removed, until a part of the conductive spacer has been exposed. The remaining portion of the second and first material layers is removed, to expose the first conductive layer and the conductive spacer. The first conductive layer and the conductive spacer, together then form a floating gate. A dielectric film layer is then formed on the substrate, and a second conductive layer is subsequently formed above the dielectric film layer.
According to a preferred embodiment of the present invention, the step of removing a portion of the second material layer also includes simultaneously removing the top edge of the conductive spacer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5427968 (1995-06-01), Hong
patent: 5474947 (1995-12-01), Chang et al.
patent: 5476801 (1995-12-01), Keshtbod
patent: 5702965 (1997-12-01), Kim
patent: 5756384 (1998-05-01), Tseng
patent: 6172394 (2001-01-01), Nakagawa

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