Method of fabricating a flash memory

Details Method of fabricating a flash memory Method of fabricating a flash memory

1999-07-29

2001-03-27

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S230000, C438S257000

Reexamination Certificate

active

06207501

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a method of fabricating a flash memory, and more particularly to a process for fabricating a flash memory with the advantages of photo masks saving, cost lowing, and throughput improving.
(2) Description of the Related Art
The flash memory is the most potential memory in the semiconductor industry. The flash memory can not only write and erase data, but also store data without volatility. The structure of a flash EEPROM (Flash Electrically Erasable Programmable Read Only memory) is that a floating gate is located between a source and a drain and there is a tunneling oxide layer between the float gate and the substrate. An electric voltage source is provided to push electrons to the floating gate, and a channel will be induced by the electrons in the float gate. The electrons are trapped in the floating gate because of the potential barrier, and are valid for storing data.
Referring now to
FIG. 1A
to
FIG. 1F
, a process for fabricating a flash cell array and its peripheral supporting circuits in accordance with a prior art is shown. Two processes of photo masks are needed for forming the gate structure of the flash memories and the peripheral PMOSs and NMOSs. After that, four processes of photo masks are needed for performing the ion implantation processes for NLDD, PLDD, N
+
, and P
+
. Firstly, referring now to
FIG. 1A
, a P-type semiconductor substrate
10
, with a flash memory area A, an NMOS area B, and a PMOS area C in an N well
11
, is provided. In addition, a layer of pad oxide
12
and a layer of field oxide
13
are also formed on the substrate
10
. A polysilicon layer
20
and a dielectric layer
21
with oxide
itride/oxide (ONO) structure are then formed at the flash memory area A of the substrate
10
. The polysilicon layer
20
is going to be the floating gate of the flash memory. After that, a layer of polysilicon
22
, a layer of tungsten silicide
23
, and a layer of TEOS
24
are formed on the substrate
10
in sequence. The first layer of photo resist
30
is then formed to protect the NMOS area B and the PMOS area C, and to define the gate pattern of the flash cell array. Referring now to
FIG. 1B
, the gate structure a of the flash cell array is formed by using the method of etching. Thereafter, a process of ion implantation is performed to form the source/drain
31
structure of the flash memory. The first layer of photo resist
30
is then stripped. After that, the second layer of photo resist
40
is formed to define the gate pattern at the NMOS area B and the PMOS area C. The gate structure b at the NMOS area B and the gate structure c at the PMOS area C are formed by using the method of etching. The second layer of photo resist
40
is then stripped.
Referring now to
FIG. 1C
, the third layer of photo resist
50
is formed to protect the PMOS area C and the flash memory area A, and the NLDD
51
at the NMOS area B is formed by a process of ion implantation
55
. The third layer of photo resist
50
is then stripped. Referring now to
FIG. 1D
, the fourth layer of photo resist
60
is formed to protect the NMOS area B and the flash memory area A, and the PLDD
61
at the PMOS area C is formed by a process of ion implantation
65
. The fourth layer of photo resist
60
is then stripped.
Referring now to
FIG. 1E
, a gate sidewall
90
is formed. After that, a fifth layer of photo resist
70
is formed to protect the PMOS area C and the flash memory area A. A process of ion implantation
75
is then performed to form the source/drain structure
71
at the NMOS area B. The fifth layer of photo resist
70
is then stripped. Referring now to
FIG. 1F
, a sixth layer of photo resist
80
is formed to protect the NMOS area B and the flash memory area A. A process of ion implantation
85
is performed to form the source/drain structure
81
at the PMOS area C. The sixth layer of photo resist
80
is then stripped. The flash memory and its peripheral NMOSs and PMOSs are then finished.
As mentioned above, in accordance with the prior art, six processes of photo masks are needed to fabricate a flash memory and its peripheral circuits. It is cost-wasting and time-wasting. In accordance with the present invention, only three or four processes of photo masks are needed. The cost could be lowered and the throughput could be improved.
SUMMARY OF THE INVENTION
According, it is a primary object of the present invention to provide a method of fabricating a flash memory with the advantages of photo masks saving, cost lowing, and throughput-improving.
These objects are accomplished by the fabrication process described below. Firstly, a P-type silicon substrate with an N-well, a layer of pad oxide, and a layer of field oxide is divided into a PMOS area, an NMOS area, and a flash memory area. After that, the first polysilicon layer and the first oxide layer are formed at the flash memory area. Thereafter, the second polysilicon layer, the second oxide layer, and a layer of TEOS are formed on the whole substrate. The first layer of photo resist is then formed to define the gate pattern of the flash cell array, and then the first process of N
+
ion implantation is performed to form the source and drain of the flash cell array. After stripping the first layer of photo resist, the second layer of photo resist is formed to define the gate pattern at the NMOS area, and then the second process of N
−
ion implantation is performed to form the LDD structure at the NMOS area.
After stripping the second layer of photo resist, the first sidewall is formed, and then the third process of N
+
ion implantation is performed at the NMOS area to form the NMOS source/drain structure. The third layer of photo resist is then formed to protect the NMOS area and the flash memory area, and the gate pattern at the PMOS area is also defined. Thereafter, the fourth process of P
−
ion implantation is performed to form the PLDD structure at the PMOS area, and then the third layer of photo resist is stripped. The second sidewall is formed, and then the fourth layer of photo resist is formed. Thereafter, the fifth process of P
+
ion implantation is performed to form the source/drain structure at the PMOS area. Finally, the fourth layer of photo resist is stripped, and the method of manufacturing a flash memory is then finished.


REFERENCES:
patent: 5897348 (1999-04-01), Wu
patent: 5911105 (1999-06-01), Sasaki

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