Method of fabricating a feature in an integrated circuit...

Details Method of fabricating a feature in an integrated circuit... Method of fabricating a feature in an integrated circuit...

1997-11-10

2001-02-13

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Masking

Subphotolithographic processing

C438S450000, C438S251000

Reexamination Certificate

active

06187694

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor processing and more particularly to a method of fabricating a feature in an integrated circuit.
BACKGROUND OF THE INVENTION
A desire to increase the speed and density of integrated circuits (ICs) has led to progressive reductions in feature dimensions, particularly in the lengths of Metal-Oxide-Semiconductor (MOS) transistor gate electrode. However, the reduction in feature dimensions is limited by a need to provide some margin for process variation, which is responsible for a difference between the target dimension and the minimum actual dimension typically yielded by the fabrication process. For example, given the process variation of conventional photolithography, it is difficult to manufacture MOS transistor gate electrodes with a target dimension of less than 250 nm using conventional photolithography to define the target dimension. To overcome this difficulty, a process of gate definition referred to as “Spacer Gate” or “SG” has been developed.
An example of an SG process flow on a semiconductor wafer is illustrated in
FIGS. 1
a
through
1
g
, each of which represent a cross sectional view of the wafer.
FIG. 1
a
shows a silicon substrate
101
. A gate oxide layer
102
has been formed on silicon substrate
101
. A polysilicon layer
103
has been formed on gate oxide layer
102
. The gate electrode of the future MOS transistor will be formed from polysilicon layer
103
.
FIG. 1
b
shows an area
104
of a silicon dioxide edge definition layer. Edge definition area
104
has been formed by patterning a layer of silicon dioxide using conventional photolithography and etch. The patterning of edge definition area
104
constitutes the first masking step of this SG process.
FIG. 1
c
shows a silicon nitride spacer layer
105
that has been formed on the wafer.
FIG. 1
d
shows silicon nitride spacers
106
and
107
that have been formed on the edge of edge definition area
104
by an anisotropic etch of spacer layer
105
.
FIG. 1
e
shows the wafer after edge definition area
104
has been etched away.
In
FIG. 1
e
, spacers
106
and
107
remain on the wafer, as part of a continuous ring of silicon nitride that was formed around the entire edge of edge definition area
104
. Since the area of gate electrode layer
103
that is covered by silicon nitride will not be subsequently removed, but the desired pattern of the gate electrode is not a continuous ring, a portion of the silicon nitride ring must be removed. The removal of a portion of the silicon nitride ring is referred to as nitride trim, which constitutes the second masking step of this SG process. In
FIG. 1
e
, spacer
106
covers an area of polysilicon layer
103
that will become a portion of a gate electrode, but spacer
107
represents a portion of the spacer ring that must be trimmed.
Figure 1
f
shows spacer
106
covered by a photoresist trim mask
108
which is formed by conventional photolithography.
FIG. 1
g
shows the wafer after spacer
107
has been removed by a trim etch and trim mask
108
has been stripped. The area of polysilicon layer
103
that is under spacer
106
will become a gate electrode with a length that depends on the length
109
of spacer
106
. The length
109
of spacer
106
depends the thickness of former spacer layer
105
, so only features of the same length as the future gate electrode can be defined with this SG process. Therefore, a third masking step is needed to define features from polysilicon layer
103
that are of greater length than the future gate electrode. Such features might include transistor gate electrodes of greater than minimum length, polysilicon interconnect lines, and polysilicon contact pads. The photoresist mask used for this third masking step is referred to as pad mask.
FIG. 1
h
shows pad mask
110
masking an area of polysilicon layer
103
that will be protected during polysilicon etch to form a contact pad.
FIG. 1
i
shows gate electrode
111
and contact pad
112
after polysilicon etch. Next, pad mask
110
is stripped. Seal oxide
113
, shown in
FIG. 1
j
, is grown to protect the edges of gate electrode
111
during subsequent processing. Finally,
FIG. 1
k
shows the wafer after spacer
106
has been etched away. The remainder of the transistor structure can be formed using conventional MOS processing.
The described method of fabricating a gate electrode using a spacer requires three masking steps. Process complexity and cost are directly related to the number of masking steps. Therefore, a method of fabricating a feature using a spacer and requiring only two masking steps is desired.
SUMMARY OF THE INVENTION
A method of fabricating a feature on a substrate is disclosed. First, a feature layer is formed on the substrate. Next, a first edge definition layer comprising a first material is formed on the feature layer. Then, a patterned second edge definition layer comprising a second material is formed on the first edge definition layer. Then, a spacer is formed adjacent to an edge of the patterned second edge definition layer. Finally, an area of the feature layer that is not under the spacer is etched to form the feature under the spacer.


REFERENCES:
patent: 4744859 (1988-05-01), Hu et al.
patent: 5466615 (1995-11-01), Tsai
patent: 5494837 (1996-02-01), Subramanian et al.
patent: 5496756 (1996-03-01), Sharma et al.
patent: 5510281 (1996-04-01), Ghezzo et al.
patent: 5610099 (1997-03-01), Stevens et al.
Stanley Wolf and Richard Tauber, Silicon Processing for hte VLSI Era vol. 1, pp. 522-523, 1986.
J.T. Horstmann, et al.; “Characterizzation of Sub-100 nm-MOS-Transistors Processed by Optical Lithography and a Sidewall-Etchback Technique”; Faculty of Electrical Engineering, University of Dortmund, Emil-Frigge-Str. 68, D 44221 Dortmun, Germany; 4 pages total.

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