Method of fabricating a dynamic random access memory device...

Details Method of fabricating a dynamic random access memory device... Method of fabricating a dynamic random access memory device...

1997-03-27

2003-10-07

Meier, Stephen D. (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S241000, C438S253000, C438S396000

Reexamination Certificate

active

06630378

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor memory device, and more particularly to a method of fabricating a dynamic random access memory device having stacked capacitor memory cell arrays.
Generally, in fabricating a dynamic random access memory device having stacked capacitor memory cell arrays, transistors have been formed before stacked capacitor memory cells are then formed. In order to form the stacked capacitor memory cells, it is necessary to carry out a large number of heat treatments. This means that a large number of heat treatments are carried out after the transistors have already been formed. For example, a reflow process is carried out to planarize an inter-layer insulator to be formed between a gate electrode and a capacitor storage electrode. An impurity diffusion process is carried out to reduce a resistivity of a stacked capacitor electrodes. A thermal oxidation process is further carried out to form a capacitor insulation film. Such heat treatments are generally carried out at a temperature, for example, in the range of 800° C. to 950° C. An approximate total time of the heat treatments is 120 minutes. Such high temperature heat treatments for a long time period cause impurity diffusions from source/drain diffusion regions whereby the source/drain diffusion regions are made deep and expand in lateral directions. As a result, it becomes likely to cause a reduction of a threshold voltage of the transistor due to short channel effects. In order to avoid this problem with the short channel effects, it is necessary to so design that a channel length defined as a distance between the source and drain regions be not shorter than a critical channel length. A possible reduction in the channel length of the transistor is important for improvement in the switching speed of the transistor. The limitation of the reduction in the channel length of the transistor results in a limitation in improvement in the high speed switching performance of the transistors such as transistors for peripheral circuits, for example, word drivers and timing generators. In order to try to settle the above problems, a technique was proposed for fabricating the dynamic random access memory device having stacked capacitor memory cell arrays. This technique is disclosed in the Japanese laid-open patent publication No. 4-134859. This technique will then be described in detail with reference to
FIGS. 1A through 1E
which are fragmentary cross sectional elevation views illustrative of a conventional method of fabricating a dynamic random access memory device having stacked capacitor memory cell arrays. The dynamic random access memory device has a memory cell area and a peripheral circuit area including a CMOS circuit. The memory cell array area and an n-channel MOS field effect transistor of the CMOS circuit are illustrated while a p-channel MOS field effect transistor of the CMOS circuit is not illustrated.
With reference to
FIG. 1A
, a p-well
2
and an n-well
3
are formed over a p-type silicon substrate
1
. Over the p-well
2
and the n-well
3
, field oxide films
4
are selectively formed by a local oxidation of silicon method. An ion-implantation of impurity is carried out to control a threshold voltage. A gate oxide film
5
is then formed by a thermal oxidation of silicon method. A phosphorus-doped polysilicon film is entirely deposited over the wafer so that the phosphorus-doped polysilicon film extends over the field oxide films
4
and the gate oxide film
5
. The phosphorus-doped polysilicon film has a thickness of 300 nanometers. The phosphorus-doped polysilicon film is then patterned to form gate electrodes
6
A and
6
B. By use of the gate electrodes
6
A and
6
B and the field oxide films
4
as masks, an ion-implantation of phosphorus is carried out at a dose of 1×10
13
cm
−2
to form phosphorus doped regions. A heat treatment to the substrate is carried out to cause a phosphorus diffusion to thereby form n
−
-type diffusion layers
7
. A first silicon oxide film
8
is then entirely deposited by a chemical vapor deposition method. The first silicon oxide film
8
extends over the field oxide films
4
, the gate electrodes
6
A and
6
B and the n
−
-type diffusion layers
7
. The first silicon oxide film
8
has a thickness of 200 nanometers. The first silicon oxide film
8
is to serve as an inter-layer insulator between MOS transistors and stacked capacitors which will be formed later. The n
−
-type diffusion layers
7
serve as source/drain diffusion regions of the MOS transistors.
With reference to
FIG. 1B
, the first silicon oxide film
8
is selectively etched to form stacked capacitor storage electrode contacts
11
over the n
−
-type diffusion layers
7
adjacent to the field oxide films
4
. Other phosphorus-doped polysilicon film is entirely deposited over the wafer so that the other phosphorus-doped polysilicon film is entirely deposited over the wafer so that the other phosphorus-doped polysilicon film extends over the n
−
-type diffusion layers
7
shown through the stacked capacitor storage electrode contacts
11
and over the first silicon oxide film
8
. The other phosphorus-doped polysilicon film has a thickness of 400 nanometers. The phosphorus-doped polysilicon film is then patterned to form stacked capacitor storage electrodes
12
which extends within the stacked capacitor storage electrode contacts
11
to contact with the n
−
-type diffusion layers
7
shown through the stacked capacitor storage electrode contacts
11
as well as over parts of the first silicon oxide film
8
overlying the gate electrodes
6
A. A silicon nitride film is entirely deposited for subsequent oxidation thereof in a steam atmosphere at a temperature of 950° C. for 20 minutes to thereby form a stacked capacitor insulation film
13
. Still another phosphorus-doped polysilicon film is entirely deposited over the wafer so that the still other phosphorus-doped polysilicon film extends over the stacked capacitor insulation film
13
. The still other phosphorus-doped polysilicon film has a thickness of 200 nanometers. A photo-resist
15
is formed over the still other phosphorus-doped polysilicon film. By use of the photo-resist
15
as a mask, the stacked capacitor insulation films
13
and the still other phosphorus-doped polysilicon film are etched to form the stacked capacitor insulation film
13
and stacked capacitor opposite electrode
14
. The stacked capacitor insulation films
13
extend over the stacked capacitor storage electrodes
12
and parts of the first silicon oxide film
8
adjacent to the stacked capacitor storage electrodes
12
. The stacked capacitor opposite electrodes
14
extend over the stacked capacitor insulation films
13
. As a result, the stacked capacitor has been fabricated, which comprises the stacked capacitor storage electrode
12
, the stacked capacitor insulation films
13
and the stacked capacitor opposite electrode
14
.
With reference to
FIG. 1C
, by use of the photo-resist
15
as a mask, the first silicon oxide film
8
is then subjected to etch-back to form side wall oxide films
17
on opposite side walls of the gate electrode
6
B. Namely, the remaining first silicon oxide films
8
on opposite side walls of the gate electrode
6
B serve as the side wall oxide films
17
.
With reference to
FIG. 1D
, the used photo-resist
15
is removed before another photo-resist
16
is selectively formed on a memory cell array area except on a peripheral circuit area. By use of the photo-resist
16
, the gate electrode
6
B and the side wall oxide films
17
as masks, an ion-implantation of arsenic is carried out at a dose of 3×10
15
cm
−2
to form n
+
-diffusion layers
18
in the p-well
2
in the peripheral circuit area. As a result, an n-channel MOS field effect transistor having a lightly doped drain structure has been fabricated in the p-well
2
in the peripheral circuit area. The used photo-resist
16
is then remov

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