Method of fabricating a dynamic random access memory capacitor

Details Method of fabricating a dynamic random access memory capacitor Method of fabricating a dynamic random access memory capacitor

1998-12-17

2001-03-20

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S255000

Reexamination Certificate

active

06204108

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87111581, filed Jul. 16, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming a capacitor.
2. Description of Related Art
Dynamic Random Access Memory (DRAM) devices are used in wide range of electronics applications. DRAMs are designed mainly for the purpose of storing data. The operations on a memory device includes reading the data stored in the device, writing (or storing) data in the device, and refreshing the data periodically.
A capacitor being charged/discharged to determine a logic 1 or a logic 0 is incorporated in a DRAM cell. Due to the increasing number of semiconductor elements incorporated in integrated circuits, the size of DRAM cell is decreased. As the size of DRAM memory cell is decreased, the effective area available for forming capacitors decreases. As a consequence, the capacitors are formed with a shrunk surface area, that is, a contact area with a decreased capacitance. As the capacitance is reduced, the capacity of a datum stored in a DRAM cell is decreased.
FIG. 1
is a cross-sectional view of a portion of semiconductor device showing a conventional hemi-spherical grain capacitor.
In
FIG. 1
, a semiconductor substrate having a source/drain region
104
is provided. An isolation layer
106
is formed on the semiconductor substrate
100
. A via opening
110
is formed in the isolation layer
106
to expose the source/drain region
104
. A crown-shape bottom storage node
108
is formed over on the isolation layer
106
to fill the via opening
110
. A hemi-spherical grain structure is formed only on the bottom inner side wall of the bottom storage node
108
. With the formation of the hemi-spherical grain structure, the effective contact area of the bottom storage node
108
is increased. With an increased effective contact area, the capacitance of capacitor is increased.
In the conventional capacitor, the hemi-spherical grain structure
110
is not formed on the inner surfaces of the bottom storage node
108
. Thus, the increase of the effective contact area is limited. As a consequence, the increase of capacitance is limited as well.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide an improved method of fabricating a capacitor with an enhanced capacity of data storage. A crown-shape bottom storage node is formed on the source/drain region. The crown-shape bottom storage node is formed with a wavelike interior surface and an outer surface with a hemispherical grain structure. With the wavelike interior surface and the hemispherical on the outer surface, the bottom storage node has an effectively increased contact area.
It is an object of the invention to provide a method for forming a capacitor to coupled with a conductive region on a substrate. A dielectric layer and a barrier layer are formed with an opening to expose the conductive region. The opening is filled with a conductive plug, while the barrier layer is covered by a first polysilicon layer. A hemi-spherical grain structure is formed on the first polysilicon layer. A composite layer comprises several different material layers is formed on the hemi-spherical grain structure. The composite layer and the first polysilicon layer are etched. The remaining composite layer and the first polysilicon layer aligned over the conductive region with a substantially smooth side surface. The composite layer is further etched by wet etching, so that portions of the composite and the first polysilicon layer are removed to formed a wavelike side surface. A second polysilicon layer is formed to cover the composite layer and is conformal to the wavelike side surface. The composite layer is removed to leave the remaining first polysilicon layer and the second polysilicon layer as a bottom electrode. A dielectric layer and a top electrode are formed to cover the bottom electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5278091 (1994-01-01), Fazan et al.
patent: 5814549 (1998-09-01), Wu
patent: 5843822 (1998-12-01), Hsia et al.
patent: 5907774 (1999-05-01), Wise

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